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    Non-volatile cache in disk drive emulation
    5.
    发明授权
    Non-volatile cache in disk drive emulation 有权
    磁盘驱动器仿真中的非易失性缓存

    公开(公告)号：US08024515B2

    公开(公告)日：2011-09-20

    申请号：US11952534

    申请日：2007-12-07

    申请人： Daniel J. Auerbach ,  Spencer W. Ng

    发明人： Daniel J. Auerbach ,  Spencer W. Ng

    IPC分类号： G06F13/00

    CPC分类号： G06F12/0804 ,  G06F3/061 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0656 ,  G06F3/068 ,  G06F12/0866 ,  G06F2212/221 ,  G06F2212/222 ,  G06F2212/461 ,  Y02D10/13 ,  Y02D10/154

    摘要： A method and apparatus for deferring media writes for emulation drives are provided. By deferring media writes using non-volatile storage, the performance penalty associated with RMW operations may be minimized. Deferring writes may allow the RMW operations to be done while the disk drive is idle. Further, deferring writes may also allow data blocks to be accumulated over time, allowing a full (4K) disk drive block size to be written with a simple write operation, thus making a RMW unnecessary.

    摘要翻译： 提供了用于推迟用于仿真驱动器的媒体写入的方法和装置。 通过使用非易失性存储推迟媒体写入，可能会使与RMW操作相关的性能损失最小化。 延迟写入可能允许在磁盘驱动器空闲时完成RMW操作。 此外，延迟写入还可以允许随时间累积数据块，从而允许用简单的写入操作来写入完整的（4K）磁盘驱动器块大小，从而使得RMW不必要。

    Method and apparatus for communicating data between a host and a plurality of parallel processors
    6.
    发明授权
    Method and apparatus for communicating data between a host and a plurality of parallel processors 失效
    用于在主机和多个并行处理器之间传送数据的方法和装置

    公开(公告)号：US4794516A

    公开(公告)日：1988-12-27

    申请号：US794354

    申请日：1985-10-31

    申请人： Daniel J. Auerbach ,  Tien C. Chen ,  Wolfgang J. Paul

    发明人： Daniel J. Auerbach ,  Tien C. Chen ,  Wolfgang J. Paul

    IPC分类号： G06F15/16 ,  G06F13/362 ,  G06F13/374 ,  G06F15/177 ,  G06F13/14

    CPC分类号： G06F13/374 ,  G06F13/362

    摘要： In a centrally controlled resource arbitration system, each of the units concurrently requesting access sends its identity code and the binary complement thereof to a central arbitration processor. The identity codes are logically combined into a first word, and the binary complements are logically combined into a second word. A subset identifier of the requesting units is then formed by combining corresponding bits of the first and second words. Unresolved values in the subset identifier are iteratively removed to eliminate a subset of the requesting units. When all but one of the requesting units have been eliminated, access to the resource is given to the remaining unit.

    摘要翻译： 在中央控制的资源仲裁系统中，同时请求访问的每个单元将其身份代码及其二进制补码发送到中央仲裁处理器。 身份码在逻辑上组合成第一个单词，二进制补码逻辑组合成第二个单词。 然后通过组合第一和第二个字的相应位来形成请求单元的子集标识符。 迭代地删除子集标识符中未解析的值以消除请求单元的子集。 当除了一个请求单元之外的所有单元已经被消除时，对剩余单元的访问资源被给予。

    High-performance multiple port memory
    7.
    发明授权
    High-performance multiple port memory 失效
    高性能多端口存储器

    公开(公告)号：US4766535A

    公开(公告)日：1988-08-23

    申请号：US811624

    申请日：1985-12-20

    申请人： Daniel J. Auerbach ,  Tien C. Chen ,  Wolfgang J. Paul

    发明人： Daniel J. Auerbach ,  Tien C. Chen ,  Wolfgang J. Paul

    IPC分类号： G06F12/06 ,  G06F9/30 ,  G06F12/04 ,  G06F15/78 ,  G06F12/00 ,  G06F13/00 ,  G06F13/38

    CPC分类号： G06F9/30138 ,  G06F15/8053

    摘要： Disclosed is a multiple port memory apparatus responsive to r+w addresses within an instruction cycle for supplying data read from the r read addresses and for writing data received to the w write addresses. The memory apparatus comprises r groups of w+1 memory banks, responsive to the r read addresses and the w write addresses, for supplying for each of the r read addresses data read from one of the w+1 banks in one of the r groups and for writing data received to each of the w write addresses in the other of the w+1 banks in the r groups. A pointer for controlling the r groups of w+1 memory banks directs the read and write accesses to the memory banks so that one of the w+1 banks obtaining valid data is read in response to a read address and so that data is written to the other banks in each cycle.The pointer directs memory accessing to prevent conflicts. Conflicts are always avoided because one bank in each of the r groups is directed to supply data in response to a read address and the w remaining banks are available for writing data in response to the w write addresses redundantly so that each of the groups of memory banks will have valid data in at least one of its w+1 memory banks for a given address.

    摘要翻译： 公开了一种响应于指令周期内的r + w地址的多端口存储器装置，用于提供从r个读取地址读取的数据并将接收到的数据写入w个写入地址。 存储器装置包括r组的w + 1个存储体，响应于r个读取地址和w个写入地址，为r个读取地址中的每一个提供从r组中的一个中的w + 1个存储体之一读取的数据 并且用于将接收到的数据写入r组中的另一个w + 1个存储体中的每个w写地址。 用于控制w + 1个存储器组的r组的指针指示对存储体的读取和写入访问，以便响应于读取地址读取获得有效数据的w + 1组之一，并且将数据写入 其他银行在每个周期。 指针指示内存访问以防止冲突。 总是避免冲突，因为r组中的每个组中的一个组针对读取地址而提供数据，并且w个剩余存储体可用于冗余地响应于w写入地址而写入数据，使得存储器组中的每一组 银行将在给定地址的至少其中一个w + 1存储器中存储有效数据。