公开(公告)号：US20100291761A1

公开(公告)日：2010-11-18

申请号：US12724584

申请日：2010-03-16

申请人： Peter Storck ,  Thomas Buschhardt

发明人： Peter Storck ,  Thomas Buschhardt

IPC分类号： H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02658 ,  Y10S438/933

摘要： A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.

摘要翻译： 一种用于制造具有正面和背面的硅单晶基板和沉积在正面上的SiGe层的晶片的方法，该方法使用以下顺序的步骤：同时抛光硅的正面和背面 单晶基板; 在所述硅单晶衬底的背面上沉积应力补偿层; 抛光硅单晶衬底的正面; 清洗具有沉积在背面的应力补偿层的硅单晶衬底; 以及在硅单晶衬底的正面上沉积完全或部分弛豫的SiGe层。

公开(公告)号：US08093143B2

公开(公告)日：2012-01-10

申请号：US12724584

申请日：2010-03-16

申请人： Peter Storck ,  Thomas Buschhardt

发明人： Peter Storck ,  Thomas Buschhardt

IPC分类号： H01L21/36

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/02658 ,  Y10S438/933

摘要： A method for producing a wafer with a silicon single crystal substrate having a front and a back side and a layer of SiGe deposited on the front side, the method using steps in the following order: simultaneously polishing the front and the back side of the silicon single crystal substrate; depositing a stress compensating layer on the back side of the silicon single crystal substrate; polishing the front side of the silicon single crystal substrate; cleaning the silicon single crystal substrate having the stress compensating layer deposited on the back side; and depositing a fully or partially relaxed layer of SiGe on the front side of the silicon single crystal substrate.

摘要翻译： 一种用于制造具有正面和背面的硅单晶基板和沉积在正面上的SiGe层的晶片的方法，该方法使用以下顺序的步骤：同时抛光硅的正面和背面 单晶基板; 在所述硅单晶衬底的背面上沉积应力补偿层; 抛光硅单晶衬底的正面; 清洗具有沉积在背面的应力补偿层的硅单晶衬底; 以及在硅单晶衬底的正面上沉积完全或部分弛豫的SiGe层。

公开(公告)号：US20140048848A1

公开(公告)日：2014-02-20

申请号：US14114056

申请日：2012-05-23

申请人： Peter Storck ,  Guenter Sachs ,  Ute Rothammer ,  Sarad Bahadur Thapa ,  Helmut Schwenk ,  Peter Dreier ,  Frank Muemmler ,  Rudolf Mayrhuber

发明人： Peter Storck ,  Guenter Sachs ,  Ute Rothammer ,  Sarad Bahadur Thapa ,  Helmut Schwenk ,  Peter Dreier ,  Frank Muemmler ,  Rudolf Mayrhuber

IPC分类号： H01L21/02 ,  H01L29/205 ,  H01L21/78

CPC分类号： H01L21/02587 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0254 ,  H01L21/02573 ,  H01L21/02617 ,  H01L21/0262 ,  H01L21/78 ,  H01L29/205

摘要： A layered semiconductor substrate has a monocrystalline first layer based on silicon, having a first thickness and a first lattice constant a1 determined by a first dopant element and a first dopant concentration, and in direct contact therewith, a monocrystalline second layer based on silicon, having a second thickness and a second lattice constant a2, determined by a second dopant element and a second dopant concentration, and a monocrystalline third layer comprising a group III nitride, the second layer located between the first layer and the third layer, wherein a2>a1, wherein the crystal lattice of the first layer and the second layer are lattice-matched, and wherein the bow of the layered semiconductor substrate is in the range from −50 μm to 50 μm.

摘要翻译： 分层半导体衬底具有基于硅的单晶第一层，其具有由第一掺杂剂元素和第一掺杂剂浓度确定的第一厚度和第一晶格常数a1，并且与第一掺杂剂浓度直接接触，基于硅的单晶第二层，其具有 由第二掺杂剂元素和第二掺杂剂浓度确定的第二厚度和第二晶格常数a2以及包含III族氮化物的单晶第三层，第二层位于第一层和第三层之间，其中a2> a1 其中，所述第一层和所述第二层的晶格是晶格匹配的，并且其中所述层状半导体衬底的所述弓形在-50μm至50μm的范围内。

公开(公告)号：US20090236696A1

公开(公告)日：2009-09-24

申请号：US12406258

申请日：2009-03-18

申请人： Peter Storck ,  Martin Vorderwestner

发明人： Peter Storck ,  Martin Vorderwestner

IPC分类号： H01L29/161 ,  H01L21/20

CPC分类号： H01L21/02532 ,  C30B25/183 ,  C30B29/52 ,  H01L21/0245 ,  H01L21/0251

摘要： A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

摘要翻译： 多层半导体晶片具有具有第一面和第二面的基板晶片; 沉积在衬底晶片的第一侧上的完全或部分松弛的异质外延层; 以及沉积在基板晶片的第二侧上的应力补偿层。 多层半导体晶片通过包括在基板的第一侧上以沉积温度沉积完全或部分松弛的异质外延层的方法制造; 并且在相同的温度下或在从沉积温度显着冷却晶片之前，在衬底的第二侧上提供应力补偿层。

公开(公告)号：US20100019278A1

公开(公告)日：2010-01-28

申请号：US12568882

申请日：2009-09-29

申请人： Peter Storck

发明人： Peter Storck

IPC分类号： H01L29/165 ,  H01L21/20

CPC分类号： H01L21/0262 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/0251 ,  H01L21/02532

摘要： A multilayer structure, comprises a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon having the composition Si1-xGex and having a lattice constant which differs from the lattice constant of silicon, and a thin interfacial layer deposited on the SiGe layer and having the composition Si1-yGey, which thin interfacial layer binds threading dislocations, and at least one further layer deposited on the interfacial layer.

摘要翻译： 一种多层结构，包括衬底和其上具有异质外延沉积的硅和锗（SiGe层）层，其具有组成为Si1-xGex并且具有不同于硅的晶格常数的晶格常数，以及沉积在SiGe上的薄界面层 并且具有组合物Si1-yGey，其薄界面层结合穿透位错，以及沉积在界面层上的至少一个另外的层。

公开(公告)号：US20080241519A1

公开(公告)日：2008-10-02

申请号：US12055356

申请日：2008-03-26

申请人： Thomas Schroeder ,  Peter Storck ,  Hans-Joachim Muessig

发明人： Thomas Schroeder ,  Peter Storck ,  Hans-Joachim Muessig

IPC分类号： H01L23/00 ,  C30B15/14

CPC分类号： H01L21/31604 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/31691 ,  H01L21/7624 ,  Y10T428/24975 ,  Y10T428/26

摘要： A layered semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) containing substantially silicon, a first amorphous intermediate layer (2) of an electrically insulating material having a thickness of 2 nm to 100 nm, a monocrystalline first oxide layer (3) having a cubic Ia-3 crystal structure, a composition of (M12O3)1-x(M22O3)x wherein each of M1 and M2 is a metal and wherein 0≦x≦1, and a lattice constant which differs from the lattice constant of the material of the substrate wafer by 0% to 5%. The invention also relates to a process for manufacturing such semiconductor wafers by epitaxial deposition.

摘要翻译： 分层半导体晶片按照给定的顺序包含以下层：基本上含有硅的单晶衬底晶片（1），具有2nm至100nm厚度的电绝缘材料的第一非晶中间层（2），第一单晶 具有立方体Ia-3晶体结构的氧化物层（3），（M 1 -O 2 O 3 O 3）1的组成 （2）其中M 1，M 2， / SUP>和M 2是金属，并且其中0≤x≤1，并且晶格常数不同于衬底晶片的材料的晶格常数0％至5％。 本发明还涉及通过外延沉积制造这种半导体晶片的方法。

公开(公告)号：US07785706B2

公开(公告)日：2010-08-31

申请号：US12055356

申请日：2008-03-26

申请人： Thomas Schroeder ,  Peter Storck ,  Hans Joachim Muessig

发明人： Thomas Schroeder ,  Peter Storck ,  Hans Joachim Muessig

IPC分类号： H01L23/00 ,  C30B15/14

CPC分类号： H01L21/31604 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/0254 ,  H01L21/31691 ,  H01L21/7624 ,  Y10T428/24975 ,  Y10T428/26

摘要： A layered semiconductor wafer contains the following layers in the given order: a monocrystalline substrate wafer (1) containing substantially silicon, a first amorphous intermediate layer (2) of an electrically insulating material having a thickness of 2 nm to 100 nm, a monocrystalline first oxide layer (3) having a cubic Ia-3 crystal structure, a composition of (M12O3)1-x(M22O3)x wherein each of M1 and M2 is a metal and wherein 0≦x≦1, and a lattice constant which differs from the lattice constant of the material of the substrate wafer by 0% to 5%. The invention also relates to a process for manufacturing such semiconductor wafers by epitaxial deposition.

摘要翻译： 分层半导体晶片按照给定的顺序包含以下层：基本上含有硅的单晶衬底晶片（1），具有2nm至100nm厚度的电绝缘材料的第一非晶中间层（2），第一单晶 具有立方体Ia-3晶体结构的氧化物层（3），（M12O3）1-x（M22O3）x的组成，其中M1和M2各自为金属，并且其中0和n1E; x和nlE1;以及不同的晶格常数 从基板晶片的材料的晶格常数提高0％〜5％。 本发明还涉及通过外延沉积制造这种半导体晶片的方法。

公开(公告)号：US08115195B2

公开(公告)日：2012-02-14

申请号：US12406258

申请日：2009-03-18

申请人： Peter Storck ,  Martin Vorderwestner

发明人： Peter Storck ,  Martin Vorderwestner

IPC分类号： H01L21/02

CPC分类号： H01L21/02532 ,  C30B25/183 ,  C30B29/52 ,  H01L21/0245 ,  H01L21/0251

摘要： A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

摘要翻译： 多层半导体晶片具有具有第一面和第二面的基板晶片; 沉积在衬底晶片的第一侧上的完全或部分松弛的异质外延层; 以及沉积在基板晶片的第二侧上的应力补偿层。 多层半导体晶片通过包括在基板的第一侧上以沉积温度沉积完全或部分松弛的异质外延层的方法制造; 并且在相同的温度下或在从沉积温度显着冷却晶片之前，在衬底的第二侧上提供应力补偿层。

公开(公告)号：US20090236695A1

公开(公告)日：2009-09-24

申请号：US12393143

申请日：2009-02-26

申请人： Peter Storck ,  Martin Vorderwestner

发明人： Peter Storck ,  Martin Vorderwestner

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L21/02532 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251

摘要： A multilayer semiconductor wafer has a substrate wafer having a first side and a second side; a fully or partially relaxed heteroepitaxial layer deposited on the first side of the substrate wafer; and a stress compensating layer deposited on the second side of the substrate wafer. The multilayer semiconductor wafer is produced by a method including depositing on a first side of a substrate a fully or partially relaxed heteroepitaxial layer at a deposition temperature; and at the same temperature or before significantly cooling the wafer from the deposition temperature, providing a stress compensating layer on a second side of the substrate.

摘要翻译： 多层半导体晶片具有具有第一面和第二面的基板晶片; 沉积在衬底晶片的第一侧上的完全或部分松弛的异质外延层; 以及沉积在基板晶片的第二侧上的应力补偿层。 多层半导体晶片通过包括在基板的第一侧上以沉积温度沉积完全或部分松弛的异质外延层的方法制造; 并且在相同的温度下或在从沉积温度显着冷却晶片之前，在衬底的第二侧上提供应力补偿层。

公开(公告)号：US20050103261A1

公开(公告)日：2005-05-19

申请号：US11020947

申请日：2004-12-23

申请人： Wilfried Von Ammon ,  Ruediger Schmolke ,  Peter Storck ,  Wolfgang Siebert

发明人： Wilfried Von Ammon ,  Ruediger Schmolke ,  Peter Storck ,  Wolfgang Siebert

IPC分类号： C23C16/44 ,  C30B23/02 ,  H01L21/205 ,  H01L21/22 ,  C30B1/00

CPC分类号： C30B23/02 ,  C30B29/40 ,  H01L21/2205 ,  Y10S438/913 ,  Y10S438/928 ,  Y10S438/98 ,  Y10T117/10

摘要： A process for epitaxially coating the front surface of a semiconductor wafer in a CVD reactor, the front surface of the semiconductor wafer being exposed to a process gas which contains a source gas and a carrier gas, and the back surface of the semiconductor wafer being exposed to a displacement gas, wherein the displacement gas contains no more than 5% by volume of hydrogen, with the result that diffusion of dopants out of the back surface of the semiconductor wafer, which is intensified by hydrogen, is substantially avoided. With this process, it is possible to produce a semiconductor wafer with a substrate resistivity of ≦100 mΩcm and a resistivity of the epitaxial layer of >1 Ωcm without back-surface coating, the epitaxial layer of which semiconductor wafer has a resistance inhomogeneity of

摘要翻译： 一种用于在CVD反应器中外延涂覆半导体晶片的前表面的方法，将半导体晶片的前表面暴露于含有源气体和载气的处理气体，并且半导体晶片的背表面暴露 位移气体，其中置换气体含有不超过5体积％的氢，结果是基本上避免了掺杂剂从氢的强化的半导体晶片的背表面扩散出来。 通过该处理，可以制造基板电阻率<= 100mOmegacm的半导体晶片和不具有背面涂覆的>1Ω·macm的外延层的电阻率，其半导体晶片的外延层具有电阻不均匀性 <10％。