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公开(公告)号：US20060270261A1
公开(公告)日：2006-11-30
申请号：US11418460
申请日：2006-05-05
IPC分类号： H01R3/00
CPC分类号： B60R21/2037 , B60Q5/003 , H01R35/025
摘要： A housing for an airbag module for arranging on the steering wheel of a motor vehicle comprises a hinge mechanism for pivotably fixing the housing to a steering wheel and at least one fixing mechanism for additionally mounting the housing on the steering wheel in a floating manner. The hinge mechanism and the fixing mechanism are arranged at a distance from each other. The inventive housing also comprises a contact mechanism for triggering a vehicle horn. The contact mechanism is arranged at a distance from the hinge mechanism, and the housing mounted in a floating manner can be pivoted about the hinge mechanism in order to trigger the vehicle horn by applied pressure.
摘要翻译： 用于布置在机动车辆的方向盘上的用于安全气囊模块的壳体包括用于将壳体可枢转地固定到方向盘的铰链机构和用于以浮动方式将壳体附加地安装在方向盘上的至少一个固定机构。 铰链机构和固定机构彼此间隔设置。 本发明的壳体还包括用于触发车辆喇叭的接触机构。 接触机构布置在与铰链机构一定距离处，并且以浮动方式安装的壳体可绕铰链机构枢转，以通过施加的压力触发车辆喇叭。
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公开(公告)号：US07316414B2
公开(公告)日：2008-01-08
申请号：US11418460
申请日：2006-05-05
IPC分类号： B60R21/203
CPC分类号： B60R21/2037 , B60Q5/003 , H01R35/025
摘要： A housing for an airbag module for arranging on the steering wheel of a motor vehicle comprises a hinge mechanism for pivotably fixing the housing to a steering wheel and at least one fixing mechanism for additionally mounting the housing on the steering wheel in a floating manner. The hinge mechanism and the fixing mechanism are arranged at a distance from each other. The inventive housing also comprises a contact mechanism for triggering a vehicle horn. The contact mechanism is arranged at a distance from the hinge mechanism, and the housing mounted in a floating manner can be pivoted about the hinge mechanism in order to trigger the vehicle horn by applied pressure.
摘要翻译： 用于布置在机动车辆的方向盘上的用于安全气囊模块的壳体包括用于将壳体可枢转地固定到方向盘的铰链机构和用于以浮动方式将壳体附加地安装在方向盘上的至少一个固定机构。 铰链机构和固定机构彼此间隔设置。 本发明的壳体还包括用于触发车辆喇叭的接触机构。 接触机构布置在与铰链机构一定距离处，并且以浮动方式安装的壳体可绕铰链机构枢转，以通过施加的压力触发车辆喇叭。
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公开(公告)号：US08219774B2
公开(公告)日：2012-07-10
申请号：US12700975
申请日：2010-02-05
申请人： Toshiya Seki , Eiju Katsuragi , Takashi Sakaguchi
发明人： Toshiya Seki , Eiju Katsuragi , Takashi Sakaguchi
CPC分类号： G06F3/0665 , G06F3/0608 , G06F3/0644 , G06F3/0689
摘要： A storage controller having a plurality of storage device and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write access sent from an information processing apparatus to a logical area in one of the plurality of virtual volumes, respectively. The control circuit, according to a search of the plurality of pool volumes for a certain storage area in which a certain data pattern is written, release the certain storage area from mapping to a logical area in the plurality of virtual volume, so that the control circuit can use the released certain storage area for mapping to a virtual volume of the plurality of virtual volume as a destination of another write access from the information processing apparatus.
摘要翻译： 一种存储控制器，其具有多个存储装置和提供多个虚拟卷的控制电路，其中每一个具有多个存储装置的多个池卷中的存储区域可被映射以响应于 分别从信息处理装置发送到多个虚拟卷之一中的逻辑区域的写访问。 控制电路根据对其中写入某一数据模式的某个存储区域的多个池卷的搜索，释放该特定存储区域以映射到多个虚拟卷中的逻辑区域，从而控制电路 电路可以使用所释放的特定存储区域来映射到作为来自信息处理设备的另一写入访问的目的地的多个虚拟卷的虚拟卷。
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公开(公告)号：US08180989B2
公开(公告)日：2012-05-15
申请号：US13025451
申请日：2011-02-11
申请人： Toshiya Seki , Eiju Katsuragi , Takashi Sakaguchi
发明人： Toshiya Seki , Eiju Katsuragi , Takashi Sakaguchi
CPC分类号： G06F3/0665 , G06F3/0608 , G06F3/0644 , G06F3/0689
摘要： A storage controller having a plurality of storage devices and a control circuit providing a plurality of virtual volumes, to each of which a storage area in a plurality of pool volumes provided with the plurality of storage devices can be mapped for writing data in response to a write access sent from an information processing apparatus to a logical area in one of the plurality of virtual volumes, respectively. The control circuit, according to a search of the plurality of pool volumes for a certain storage area in which a certain data pattern is written, releases the certain storage area from mapping to a logical area in the plurality of virtual volumes, so that the control circuit can use the released certain storage area for mapping to a virtual volume of the plurality of virtual volumes as a destination of another write access from the information processing apparatus.
摘要翻译： 一种具有多个存储装置的存储控制器和一个提供多个虚拟卷的控制电路，每个虚拟卷都具有多个存储设备的多个池卷中的存储区域可被映射以响应于 分别从信息处理装置发送到多个虚拟卷之一中的逻辑区域的写访问。 控制电路根据对其中写入特定数据模式的某个存储区域的多个池卷的搜索，将特定存储区域从映射释放到多个虚拟卷中的逻辑区域，使得控制电路 电路可以使用释放的特定存储区域来映射到作为来自信息处理设备的另一个写入访问的目的地的多个虚拟卷中的虚拟卷。
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公开(公告)号：US20110153954A1
公开(公告)日：2011-06-23
申请号：US12527442
申请日：2009-05-15
申请人： Toshiya Seki , Takashi Sakaguchi
发明人： Toshiya Seki , Takashi Sakaguchi
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F3/062 , G06F3/0634 , G06F3/0647 , G06F3/067 , G06F12/0866 , G06F2212/263 , G06F2212/312 , G06F2212/466
摘要： Provided is a storage subsystem capable of speeding up the input/output processing for a cache memory. Microprocessor Packages manage information related to a VDEV ownership for controlling virtual devices and a cache segment ownership for controlling cache segments in units of Microprocessor Packages, and one Microprocessor among multiple Microprocessors belonging to the determined Microprocessor Package to perform input/output processing for the virtual devices searches cache control information stored in the Package Memory without searching the cache control information in the shared memory, and if data exists in the cache memory, accesses the cache memory, and if it does not, accesses the virtual devices.
摘要翻译： 提供了一种能够加速高速缓冲存储器的输入/输出处理的存储子系统。 微处理器软件包管理与用于控制虚拟设备的VDEV所有权相关的信息，以及用于以微处理器软件包为单位控制缓存段的高速缓存段所有权，以及属于确定的微处理器软件包的多个微处理器中的一个微处理器，以对虚拟设备执行输入/输出处理 搜索存储在包存储器中的高速缓存控制信息，而不搜索共享存储器中的高速缓存控制信息，并且如果高速缓冲存储器中存在数据，则访问高速缓冲存储器，如果不存在则访问虚拟设备。
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公开(公告)号：US07246208B2
公开(公告)日：2007-07-17
申请号：US10822725
申请日：2004-04-13
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F3/0601 , G06F12/0866 , G06F12/0871 , G06F2003/0697 , G06F2212/282 , G06F2212/311 , G06F2212/312 , G06F2212/6042 , Y10S707/99943
摘要： The present invention partitions a cache region of a storage subsystem for each user and prevents interference between user-dedicated regions.A plurality of CLPR can be established within the storage subsystem. A CLPR is a user-dedicated region that can be used by partitioning the cache region of a cache memory. Management information required to manage the data stored in the cache memory is allocated to each CLPR in accordance with the attribute of the segment or slot. The clean queue and clean counter, which manage the segments in a clean state, are provided in each CLPR. The dirty queue and dirty counter are used jointly by all the CLPR. The free queue, classification queue, and BIND queue are applied jointly to all the CLPR, only the counters being provided in each CLPR.
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公开(公告)号：US20060066756A1
公开(公告)日：2006-03-30
申请号：US11237858
申请日：2005-09-29
申请人： Kunio Yamagishi , Takashi Sakaguchi
发明人： Kunio Yamagishi , Takashi Sakaguchi
IPC分类号： H04N5/14
CPC分类号： H04N5/57 , G09G3/20 , G09G2320/0276 , G09G2320/0606 , G09G2320/066 , G09G2320/0673 , H04N5/202 , H04N5/4401 , H04N21/4318 , H04N21/44008
摘要： A digital Y signal compatible with a plurality of pixels in one frame unit is divided into a plurality of signal level regions for each constant signal level range by means of a histogram generator circuit, a rate of pixels included in each signal level to all the pixels is detected, and a histogram is generated. In addition, a correction coefficient is set, and the correction coefficient is stored in a correction coefficient storage circuit. In a computing circuit, a correction value relevant to a signal level in each signal level region is calculated in accordance with the histogram and correction coefficient, and input and output characteristics of the digital Y signal are adjusted on the basis of the calculated correction value. The digital Y signal is gamma-corrected by a Y-γcorrecting circuit in accordance with the input and output characteristics adjusted by the computing circuit.
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公开(公告)号：US20050269193A1
公开(公告)日：2005-12-08
申请号：US11139105
申请日：2005-05-27
申请人： Takashi Sakaguchi
发明人： Takashi Sakaguchi
CPC分类号： B60Q5/003
摘要： The invention relates to a device for actuating the horn on steering wheels, comprising a steering wheel frame and at least one fixed horn contact provided thereon, and comprising a moving paddling support i.e. generator support and at least one horn contact, which is provided thereon and to which the fixed horn contact is assigned. The invention provides that the padding support i.e. the generator support is mounted on the steering wheel frame in a manner that enables it to pivot at a position.
摘要翻译： 本发明涉及一种用于致动方向盘上的喇叭的装置，包括方向盘框架和设置在其上的至少一个固定喇叭触点，并且包括移动的划桨支撑件，即发电机支撑件和至少一个喇叭触点， 分配固定喇叭触点的位置。 本发明提供了填充支撑件，即发电机支撑件，以使其能够在一个位置枢转的方式安装在方向盘框架上。
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公开(公告)号：US5384595A
公开(公告)日：1995-01-24
申请号：US987874
申请日：1992-12-09
申请人： Takashi Sakaguchi
发明人： Takashi Sakaguchi
IPC分类号： H04N5/21 , H04N1/409 , H04N5/225 , H04N5/232 , H04N5/235 , H04N5/243 , H04N5/335 , H04N5/351 , H04N5/353 , H04N5/361 , H04N5/378 , H04N9/64 , H04N9/77 , H04N5/228
CPC分类号： H04N5/2327 , H04N5/23248 , H04N5/23254 , H04N5/23267 , H04N5/23274 , H04N5/235 , Y10S348/91
摘要： A motion detector includes a flicker compensating circuit for removing flicker components from a video signal, and a motion vector detecting circuit for detecting a motion vector in response to an output signal from the flicker compensating circuit. An image stabilizing system includes a flicker compensating circuit for removing flicker components from a video signal, a motion vector detecting circuit for detecting a motion vector in response to an output signal from the flicker compensating circuit, and a motion compensating circuit for removing motion components from the video signal in response to the motion vector detected by the motion vector detecting circuit.
摘要翻译： 运动检测器包括用于从视频信号中去除闪烁分量的闪烁补偿电路和用于响应于来自闪烁补偿电路的输出信号检测运动矢量的运动矢量检测电路。 图像稳定系统包括用于从视频信号中去除闪烁分量的闪烁补偿电路，用于响应于来自闪烁补偿电路的输出信号检测运动矢量的运动矢量检测电路，以及用于从运动补偿电路中去除运动分量的运动补偿电路 所述视频信号响应于由所述运动矢量检测电路检测到的运动矢量。
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公开(公告)号：US5321515A
公开(公告)日：1994-06-14
申请号：US894741
申请日：1992-06-05
CPC分类号： H04N19/523 , H04N5/144 , H04N5/23248
摘要： An image fluctuation correcting apparatus for correcting image fluctuations without using a field memory by providing an image fluctuation predicting circuit for predicting image fluctuation in a succeeding field from the image fluctuation determined in a preceding field and moving signal read addresses of a solid state image pickup device in accordance with the predicted value. In another image fluctuation correcting apparatus, movements of an image pickup apparatus are detected by using an acceleration detecting circuit to thereby predict image fluctuation in a succeeding field by a predicting apparatus on the basis of the detected movement of the image pickup apparatus for correcting the image fluctuation.
摘要翻译： 一种图像波动校正装置，用于通过提供图像波动预测电路来校正图像波动，而不需要使用场存储器，该图像波动预测电路用于根据在前一场中确定的图像波动预测后续图像波动，并且固态图像拾取装置的移动信号读取地址 按照预测值。 在另一个图像波动校正装置中，通过使用加速度检测电路来检测图像拾取装置的移动，从而基于检测到用于校正图像的图像拾取装置的移动来预测预测装置在后续场中的图像波动 波动。
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