公开(公告)号：US06400603B1

公开(公告)日：2002-06-04

申请号：US09564324

申请日：2000-05-03

申请人： Trevor Blyth ,  David Sowards ,  Dean Allum ,  Philip C. Barnett

发明人： Trevor Blyth ,  David Sowards ,  Dean Allum ,  Philip C. Barnett

IPC分类号： G11C1604

CPC分类号： G11C16/0425 ,  G11C16/0408 ,  G11C16/08

摘要： By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

摘要翻译： 通过减少在写入或擦除操作中必须擦除的FLASH EEPROM阵列中包含的块或页面的大小，减少所需寄存器的大小，使处理器更容易处理较小的信息块，减少 微处理器的尺寸和复杂性，并且增加了FLASH EEPROM的耐久性，从而允许其代替现有技术的EEPROM。 通过闪存EEPROM更换面罩ROM可以对代码存储区进行全面测试，并允许客户在其制造过程中使用该空间进行测试。 然后可以在最终装运前用最终代码存储来清除用于测试的代码并重新编程。

公开(公告)号：US06510081B2

公开(公告)日：2003-01-21

申请号：US10022314

申请日：2001-12-18

申请人： Trevor Blyth ,  David Sowards ,  Philip C. Barnett

发明人： Trevor Blyth ,  David Sowards ,  Philip C. Barnett

IPC分类号： G11C1604

CPC分类号： G11C16/0425 ,  G11C16/0408 ,  G11C16/08

摘要： By reducing the size of the blocks or pages that are contained in a FLASH EEPROM array that must be erased in a write or erase operation, the size of register needed is reduced, making it easier for the processor to handle smaller blocks of information, reducing the size and complexity of the microprocessor, and increasing the endurance of the FLASH EEPROM allowing it to be used in place of the state of the art EEPROM. Replacing mask ROM by flash EEPROM allows full testing of the code storage area as well as allowing customers to use that space for testing in their manufacturing procedures. The code used for testing can then be cleared and reprogrammed with the final code storage before final shipment.

公开(公告)号：US07032064B2

公开(公告)日：2006-04-18

申请号：US10376682

申请日：2003-02-28

申请人： Philip C. Barnett ,  David Sowards

发明人： Philip C. Barnett ,  David Sowards

IPC分类号： G06F12/00

CPC分类号： G11C16/30

摘要： A single chip embedded microcontroller has a processor that communicates with multiple non-volatile erasable PROMS which may be an OTPROM and an EEPROM. The processor also communicates with a high voltage generator that produces the erase and write voltages for the OTPROM and EEPROM. A switch communicates with the high voltage generator and switches the erase and write voltages alternately between the OTPROM and EEPROM. The OTPROM and EEPROM are FLASH arrays. The FLASH array technology allows the EEPROM and OTPROM to have similar erase and write voltages and therefore to share one high voltage generator. The high voltage generator is switched alternately between the first and second non-volatile erasable PROM arrays to enforce the principle that the EEPROM and OTPROM cannot be written to or erased at the same and may only be written to or erased one at a time.

公开(公告)号：US06292874B1

公开(公告)日：2001-09-18

申请号：US09420318

申请日：1999-10-19

申请人： Philip C. Barnett

发明人： Philip C. Barnett

IPC分类号： G06F1202

CPC分类号： G06F12/145

摘要： A memory management unit is disclosed for a single-chip data processing circuit, such as a smart card. The memory management unit (i) partitions a homogeneous memory device to achieve heterogeneous memory characteristics for various regions of the memory device, and (ii) restricts access of installed applications executing in the microprocessor core to predetermined memory ranges. The memory management unit provides two operating modes for the processing circuit. In a secure kernel mode, the programmer can access all resources of the device including hardware control. In an application mode, the memory management unit translates the virtual memory address used by the software creator into the physical address allocated to the application by the operating system in a secure kernel mode during installation. The memory management unit implements memory address checking using limit registers and translates virtual addresses to an absolute memory address using offset registers. The memory management unit loads limit and offset registers with the appropriate values from an application table to ensure that the executing application only accesses the designated memory locations. The memory management unit can also partition a homogeneous memory device, such as an FERAM memory device, to achieve heterogeneous memory characteristics normally associated with a plurality of memory technologies, such as volatile, non-volatile and program storage (ROM) memory segments. Once partitioned, the memory management unit enforces the appropriate corresponding memory characteristics for each heterogeneous memory type.

摘要翻译： 公开了一种用于诸如智能卡的单芯片数据处理电路的存储器管理单元。 存储器管理单元（i）对均匀的存储器件进行分区以实现存储器件的各个区域的异质存储器特性，以及（ii）将在微处理器内核中执行的安装的应用程序的访问限制到预定的存储器范围。 存储器管理单元为处理电路提供两种操作模式。 在安全的内核模式下，程序员可以访问设备的所有资源，包括硬件控制。 在应用模式中，存储器管理单元在安装期间以安全内核模式将由软件创建者使用的虚拟存储器地址转换为由操作系统分配给应用的物理地址。 存储器管理单元使用限制寄存器实现存储器地址检查，并使用偏移寄存器将虚拟地址转换为绝对存储器地址。 存储器管理单元使用来自应用表的适当值加载限制和偏移寄存器，以确保执行的应用程序仅访问指定的存储器位置。 存储器管理单元还可以分配诸如FERAM存储器设备的均匀存储器设备，以实现通常与诸如易失性，非易失性和程序存储（ROM）存储器段等多种存储器技术相关联的异构存储器特性。 一旦分区，存储器管理单元对每个异构存储器类型实施适当的对应的存储器特性。

公开(公告)号：US07464192B2

公开(公告)日：2008-12-09

申请号：US10238757

申请日：2002-09-10

申请人： Philip C. Barnett ,  Andy Green ,  Peter C. Van Buskirk

发明人： Philip C. Barnett ,  Andy Green ,  Peter C. Van Buskirk

IPC分类号： G06F3/00

CPC分类号： G06F13/385

摘要： A programmable serial interface is disclosed for use in a semiconductor circuit that supports a plurality of communication protocols. The programmable serial interface includes one or more shared hardware components that implement tasks and functions of a plurality of communication protocols, optional protocol specific hardware, a processor and memory. For each task or function required by a supported communication protocol, a determination is made as to which parts of the function will be implemented using shared hardware, protocol specific hardware or in software. The communication protocols to be supported are identified, and the functions performed in accordance with each of the supported protocols are analyzed to identify those functions suitable for common or shared hardware with other communication protocols. In addition, unique or time-critical functions are identified that must be implemented in hardware. Finally, any functions that are not implemented in hardware are implemented in software.

摘要翻译： 公开了可用于支持多个通信协议的半导体电路中的可编程串行接口。 可编程串行接口包括实现多个通信协议，可选协议特定硬件，处理器和存储器的任务和功能的一个或多个共享硬件组件。 对于支持的通信协议所需的每个任务或功能，确定将使用共享硬件，协议特定硬件或软件来实现功能的哪些部分。 识别要支持的通信协议，并且分析根据每个所支持的协议执行的功能，以识别适合于具有其他通信协议的公共或共享硬件的那些功能。 另外，确定必须以硬件实现的独特或时间关键的功能。 最后，在硬件中未实现的任何功能都是用软件实现的。

公开(公告)号：US06173419B2

公开(公告)日：2001-01-09

申请号：US09078872

申请日：1998-05-14

申请人： Philip C. Barnett

发明人： Philip C. Barnett

IPC分类号： G06F1100

CPC分类号： G06F11/3652 ,  G06F11/261

摘要： An emulator is used to debug software operating on a target micro-controller in a target circuit environment. The emulator contains a field programmable gate array that is programmed to contain an emulated target micro-controller and an emulated monitoring circuit which monitors the operations of the micro-controller. The emulated target micro-controller receives signals from the target circuit environment. The signals from the target circuit environment are communicated to the emulated target micro-controller by one or more channels, such as a data channel and a timing channel. The number of channels is limited so that signals from the target environment do not degrade the performance of the emulator. A host computer contains a software debug program which works with the emulated monitoring circuit to monitor the emulated micro-controller. The FIELD PROGRAMMABLE GATE ARRAY is programmed to have the characteristics of one or more types of memory, for example ROM, PROM and EEPROM to emulate the different types of memory.

摘要翻译： 仿真器用于在目标电路环境中调试在目标微控制器上运行的软件。 仿真器包含一个现场可编程门阵列，被编程为包含一个仿真的目标微控制器和一个监控微控制器运行的仿真监控电路。 仿真目标微控制器从目标电路环境接收信号。 来自目标电路环境的信号通过一个或多个信道（诸如数据信道和定时信道）传送到仿真的目标微控制器。 通道数量受到限制，从而来自目标环境的信号不会降低仿真器的性能。 主机包含一个软件调试程序，该程序与仿真监控电路一起工作，以监控仿真的微控制器。 现场可编程门阵列被编程为具有一种或多种类型的存储器的特性，例如ROM，PROM和EEPROM来模拟不同类型的存储器。

公开(公告)号：US06639428B2

公开(公告)日：2003-10-28

申请号：US10027665

申请日：2001-12-20

申请人： Andy Green ,  Philip C. Barnett

发明人： Andy Green ,  Philip C. Barnett

IPC分类号： G06F132

CPC分类号： G06F1/3237 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3287 ,  H03K19/0016 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/171

摘要： A digital circuit run in conjunction with a system clock signal. The digital circuit includes: a digital logic circuitry regulated by a clock signal and powered by a system current; and a clocking circuitry, communicatively coupled to the digital logic circuitry and the system clock signal, for supplying the clock signal to the digital logic circuitry. The clocking circuitry includes: a power supply monitor circuitry, communicatively coupled to the power supply, providing a first signal indicative of a predetermined level of system current; and a clock regulation circuitry, communicatively coupled to the power supply circuitry, which outputs the clock signal to the digital logic circuitry in response to the first signal. The clock signal comprises (1) the system clock signal when the first signal is in a first state, and (2) a modified clock signal when the first signal is in a second state.

摘要翻译： 数字电路与系统时钟信号一起运行。 数字电路包括：由时钟信号调节并由系统电流供电的数字逻辑电路; 以及通信地耦合到数字逻辑电路和系统时钟信号的时钟电路，用于将时钟信号提供给数字逻辑电路。 时钟电路包括：电源监视器电路，通信地耦合到电源，提供指示系统电流的预定电平的第一信号; 以及通信地耦合到电源电路的时钟调节电路，其响应于第一信号将时钟信号输出到数字逻辑电路。 时钟信号包括（1）当第一信号处于第一状态时的系统时钟信号，和（2）当第一信号处于第二状态时的修改的时钟信号。

公开(公告)号：US6145020A

公开(公告)日：2000-11-07

申请号：US78952

申请日：1998-05-14

申请人： Philip C. Barnett

发明人： Philip C. Barnett

IPC分类号： G06F15/78 ,  G06F13/00

CPC分类号： G06F15/7867 ,  G06F15/7814

摘要： The present invention is an enhanced peripheral controller communicating between a microcontroller and multiple peripherals that increases the speed with which configuration data sets are loaded. The enhanced peripheral controller includes a programmable logic array (PLA) and an FeRAM array. A reconfigurable peripheral controller is programmed onto the programmable logic array from a configuration data set for one of multiple peripherals. The reconfigurable peripheral controller is reprogrammed each time a new peripheral is connected to the microcontroller. The FeRAM array contains the configuration data set for programming the reconfigurable peripheral controller onto the programmable logic array. The FeRAM will receive a different configuration data set for each different peripheral to be programmed onto the PLA. Because the FeRAM operates at the speed of RAM, it receives the configuration data set for each peripheral on the fly as the microcontroller operates. In addition, the microcontroller and FeRAM cooperate to reprogram the reconfigurable peripheral controller on the fly for each different peripheral.

摘要翻译： 本发明是在微控制器和多个外围设备之间进行通信的增强的外围控制器，其增加了加载配置数据集的速度。 增强的外围控制器包括可编程逻辑阵列（PLA）和FeRAM阵列。 可重新配置的外围控制器由多个外设之一的配置数据组编程到可编程逻辑阵列上。 每当新的外设连接到微控制器时，可重新配置的外设控制器被重新编程。 FeRAM阵列包含用于将可重新配置的外围控制器编程到可编程逻辑阵列上的配置数据集。 FeRAM将为PLA编程的每个不同的外设接收不同的配置数据。 由于FeRAM以RAM的速度运行，所以当微控制器工作时，它会随时随地接收每个外围设备的配置数据。 此外，微控制器和FeRAM可协同重新编程每个不同外设的可重构外设控制器。

公开(公告)号：US06988231B2

公开(公告)日：2006-01-17

申请号：US09809897

申请日：2001-03-16

申请人： Philip C. Barnett

发明人： Philip C. Barnett

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G06F11/2635 ,  G01R31/3187

摘要： A semiconductor circuit is disclosed that contains test hardware or test software (or both) that allows test functions to be executed directly from the memory of the semiconductor circuit. A remote testing station can issue a command indicating a specific test function that should be implemented. The disclosed semiconductor circuit independently performs the indicated test and provides the results to the test station. For an exemplary memory test, the test hardware and test software are employed to initially clear the memory and thereafter selectively apply a pattern to memory and read the applied pattern from each address to confirm that the correct pattern has been stored. The testing technique of the present invention reduces the number of pins that must be contacted by the tester, such as the address pins. In addition, the reduced number of contact points allows a number of semiconductor circuits to be setup and tested in parallel using the same automated test equipment (ATE).

公开(公告)号：US6108236A

公开(公告)日：2000-08-22

申请号：US118736

申请日：1998-07-17

申请人： Philip C. Barnett

发明人： Philip C. Barnett

IPC分类号： G06F11/10 ,  G07F7/10 ,  G11C16/06

CPC分类号： G07F7/1008 ,  G06F11/1068 ,  G06Q20/341 ,  G07F7/084

摘要： A smart card having integrated circuitry including a single chip embedded microcontroller for controlling all processes and transactions that take place on the card. The single chip embedded microcontroller comprises a processor, a non-volatile erasable PROM communicating with the processor for reading and writing information to and from the PROM, and an error check and correction circuit cooperating with the PROM to correct errors occurring during the read and write operations after the PROM has performed a greater number of read and write cycles than its endurance. By such arrangement, the accuracy of the read and write operations on the smart card is maintained beyond the endurance of said PROM, enabling PROM-based smart cards having endurance on the order of 100,000 read and write cycles.

摘要翻译： 具有集成电路的智能卡，包括用于控制在卡上发生的所有过程和事务的单芯片嵌入式微控制器。 单芯片嵌入式微控制器包括处理器，与处理器通信的非易失性可擦除PROM，用于向PROM读取和写入信息，以及与PROM协作以纠正在读取和写入期间发生的错误的错误校验和校正电路 PROM执行的读取和写入周期比其耐久性更多的操作。 通过这样的安排，智能卡上的读写操作的精度保持在所述PROM的耐久性之上，使得基于PROM的智能卡具有100,000次读和写周期的耐久性。