公开(公告)号：US07368045B2

公开(公告)日：2008-05-06

申请号：US11050790

申请日：2005-01-27

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： C25D5/02 ,  C25D11/04

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US07868410B2

公开(公告)日：2011-01-11

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral, Jr. ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L21/70

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20080142894A1

公开(公告)日：2008-06-19

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L27/088 ,  H01L29/423

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US20090152642A1

公开(公告)日：2009-06-18

申请号：US12355368

申请日：2009-01-16

申请人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/02

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07452767B2

公开(公告)日：2008-11-18

申请号：US11500254

申请日：2006-08-07

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20110165767A1

公开(公告)日：2011-07-07

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/28

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07928514B2

公开(公告)日：2011-04-19

申请号：US12355368

申请日：2009-01-16

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L29/76

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07105889B2

公开(公告)日：2006-09-12

申请号：US10863830

申请日：2004-06-04

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L29/792

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US07745278B2

公开(公告)日：2010-06-29

申请号：US12211530

申请日：2008-09-16

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlOxNy。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包括HCl / H2O2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。