公开(公告)号：US08331134B2

公开(公告)日：2012-12-11

申请号：US12853301

申请日：2010-08-10

申请人： Pi-Feng Chiu ,  Meng-Fan Chang ,  Ku-Feng Lin ,  Shyh-Shyuan Sheu

发明人： Pi-Feng Chiu ,  Meng-Fan Chang ,  Ku-Feng Lin ,  Shyh-Shyuan Sheu

IPC分类号： G11C11/00

CPC分类号： G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C14/0054 ,  G11C14/009

摘要： A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.

摘要翻译： 提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。 第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。 第一和第二开关的第二端子分别连接到第一和第二位线。 第一和第二开关的控制端子连接到字线。 第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。 第一和第二NVM的第二端子分别连接到第一和第二位线。 第一和第二NVM的使能端子连接到使能线。

公开(公告)号：US20110280073A1

公开(公告)日：2011-11-17

申请号：US12853301

申请日：2010-08-10

申请人： Pi-Feng Chiu ,  Meng-Fan Chang ,  Ku-Feng Lin ,  Shyh-Shyuan Sheu

发明人： Pi-Feng Chiu ,  Meng-Fan Chang ,  Ku-Feng Lin ,  Shyh-Shyuan Sheu

IPC分类号： G11C14/00

CPC分类号： G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C14/0054 ,  G11C14/009

摘要： A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.

摘要翻译： 提供了包括锁存单元，第一开关，第二开关，第一非易失性存储器（NVM）和第二NVM的非易失性静态随机存取存储器（NV-SRAM）及其操作方法。 第一和第二开关的第一端子分别连接到闩锁单元的第一和第二端子。 第一和第二开关的第二端子分别连接到第一和第二位线。 第一和第二开关的控制端子连接到字线。 第一和第二NVM的第一端子分别连接到闩锁单元的第一和第二端子。 第一和第二NVM的第二端子分别连接到第一和第二位线。 第一和第二NVM的使能端子连接到使能线。

公开(公告)号：US08392132B2

公开(公告)日：2013-03-05

申请号：US12851547

申请日：2010-08-05

申请人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G06F19/00

CPC分类号： G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

摘要： A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

摘要翻译： 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US20110270555A1

公开(公告)日：2011-11-03

申请号：US12851547

申请日：2010-08-05

申请人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Ku-Feng Lin ,  Meng-Fan Chang ,  Shyh-Shyuan Sheu ,  Pei-Chia Chiang ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G06F19/00 ,  G01R19/00

CPC分类号： G01R31/2837 ,  G11C13/00 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/0409 ,  H01L22/34

摘要： A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result. The compensation signal generator is connected to the process variation detector, and produces a corresponding compensation signal according to the current comparison result.

摘要翻译： 提供了一种过程变化检测装置和工艺变化检测方法。 过程变化检测装置包括处理变化检测器和补偿信号发生器。 过程变化检测器包括第一过程变化检测部件，第二过程变化检测部件和电流比较器。 第一处理变化检测部件的通道是第一导电型，第二处理变化检测部件的通道是第二导电型，其中上述第一导电类型与第二导电类型不同。 电流比较器连接到第一处理变化检测部件和第二处理变化检测部件，用于比较两个部件之间的电流差异并输出当前的比较结果。 补偿信号发生器连接到过程变化检测器，并根据当前比较结果产生相应的补偿信号。

公开(公告)号：US20130114325A1

公开(公告)日：2013-05-09

申请号：US13332402

申请日：2011-12-21

申请人： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

发明人： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC分类号： G11C11/00 ,  G11C7/10

CPC分类号： G11C14/009

摘要： A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

摘要翻译： 提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。 第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。 第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。 第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。 第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。 开关的第二端子耦合到第三电压。

公开(公告)号：US20120320658A1

公开(公告)日：2012-12-20

申请号：US13230865

申请日：2011-09-13

申请人： Min-Chuan Wang ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

发明人： Min-Chuan Wang ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC分类号： G11C11/00

CPC分类号： G11C14/0054

摘要： A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.

摘要翻译： 提供了包括静态随机存取电路，第一存储设备，第二存储设备和开关单元的非易失性静态随机存取存储器（NVSRAM）单元。 静态随机存取电路具有分别具有第一电压和第二电压的第一端子和第二端子。 第一存储装置和第二存储装置中的存储数据由第一电压和第二电压确定。 第一存储装置和第二存储装置分别具有第一连接端子和第二连接端子。 开关单元分别耦合到第一存储装置和第二存储装置的第二连接端子，并且由开关线路的开关信号控制，以将第一存储装置和第二存储装置导向同一位线或 相同的补充位线。

公开(公告)号：US08508983B2

公开(公告)日：2013-08-13

申请号：US13230865

申请日：2011-09-13

申请人： Min-Chuan Wang ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

发明人： Min-Chuan Wang ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC分类号： G11C11/00

CPC分类号： G11C14/0054

摘要： A non-volatile static random access memory (NVSRAM) cell including a static random access circuit, first storage device, a second storage device, and a switch unit is provided. The static random access circuit has a first terminal and a second terminal respectively having a first voltage and a second voltage. Stored data in the first storage device and the second storage device are determined by the first voltage and the second voltage. The first storage device and the second storage device respectively have a first connection terminal and a second connection terminal. The switch unit is respectively coupled to the second connection terminals of the first storage device and the second storage device, and is controlled by a switching signal of a switch line to conduct the first storage device and the second storage device to a same bit line or a same complementary bit line.

摘要翻译： 提供了包括静态随机存取电路，第一存储设备，第二存储设备和开关单元的非易失性静态随机存取存储器（NVSRAM）单元。 静态随机存取电路具有分别具有第一电压和第二电压的第一端子和第二端子。 第一存储装置和第二存储装置中的存储数据由第一电压和第二电压确定。 第一存储装置和第二存储装置分别具有第一连接端子和第二连接端子。 开关单元分别耦合到第一存储装置和第二存储装置的第二连接端子，并且由切换线的切换信号控制，以将第一存储装置和第二存储装置导入相同的位线或 相同的补充位线。

公开(公告)号：US20130121058A1

公开(公告)日：2013-05-16

申请号：US13345740

申请日：2012-01-08

申请人： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G11C11/00

CPC分类号： G11C8/16 ,  G11C7/14 ,  G11C8/08 ,  G11C8/18 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

摘要： A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.

摘要翻译： 提供了用于控制非易失性存储器的写入定时的电路和方法。 该方法包括以下步骤。 首先，监视执行写入操作的非易失性存储器中的至少一个存储单元的电阻状态切换，以输出控制信号。 存储单元存储具有不同电阻状态的数据状态。 通过定时控制线将写时序输入到存储单元。 接下来，基于时钟信号和控制信号来生成写入定时。 写时序在时钟信号的周期开始时被使能，并且当存储器单元完成电阻状态切换时被禁止。

公开(公告)号：US08625361B2

公开(公告)日：2014-01-07

申请号：US13345740

申请日：2012-01-08

申请人： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

发明人： Pi-Feng Chiu ,  Shyh-Shyuan Sheu ,  Wen-Pin Lin ,  Chih-He Lin

IPC分类号： G11C7/10 ,  G11C8/16

CPC分类号： G11C8/16 ,  G11C7/14 ,  G11C8/08 ,  G11C8/18 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0078

摘要： A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.

摘要翻译： 提供了用于控制非易失性存储器的写入定时的电路和方法。 该方法包括以下步骤。 首先，监视执行写入操作的非易失性存储器中的至少一个存储单元的电阻状态切换，以输出控制信号。 存储单元存储具有不同电阻状态的数据状态。 通过定时控制线将写时序输入到存储单元。 接下来，基于时钟信号和控制信号来生成写入定时。 写时序在时钟信号的周期开始时被使能，并且当存储器单元完成电阻状态切换时被禁止。

公开(公告)号：US08422295B1

公开(公告)日：2013-04-16

申请号：US13332402

申请日：2011-12-21

申请人： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

发明人： Chih-He Lin ,  Wen-Pin Lin ,  Pi-Feng Chiu ,  Shyh-Shyuan Sheu

IPC分类号： G11C14/00

CPC分类号： G11C14/009

摘要： A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

摘要翻译： 提供了非易失性随机存取存储器（NV-RAM）及其操作方法。 NV-RAM包括锁存单元，开关和第一至第四非易失性存储元件。 第一和第三非易失性存储元件的第一端分别耦合到第一电压和第二电压。 第一非易失性存储元件的第二端子和第二非易失性存储器元件的第一端子耦合到锁存单元的第一端子。 第三非易失性存储元件的第二端子和第四非易失性存储元件的第一端子耦合到锁存单元的第二端子。 第二和第四非易失性存储元件的第二端子耦合到开关的第一端子。 开关的第二端子耦合到第三电压。