公开(公告)号：US07817466B2

公开(公告)日：2010-10-19

申请号：US12130918

申请日：2008-05-30

Applicant: Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

Inventor： Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

IPC: G11C11/34

CPC classification number: H01L27/105 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C2211/4016 ,  H01L21/8232 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/118 ,  H01L27/11803 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/7841

Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

Abstract translation: 半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。 每个单元耦合到许多控制线，允许选择和读取/写入所述单元。 所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

公开(公告)号：US20090086535A1

公开(公告)日：2009-04-02

申请号：US12130918

申请日：2008-05-30

Applicant: Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

Inventor： Richard Ferrant ,  Franck Genevaux ,  David Burnett ,  Gerald Gouya ,  Pierre Malinge

IPC: G11C11/34

CPC classification number: H01L27/105 ,  G11C11/4023 ,  G11C11/4026 ,  G11C11/405 ,  G11C2211/4016 ,  H01L21/8232 ,  H01L21/84 ,  H01L27/0207 ,  H01L27/10 ,  H01L27/1052 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10882 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/118 ,  H01L27/11803 ,  H01L27/12 ,  H01L27/1203 ,  H01L29/7841

Abstract: A semiconductor array includes a matrix of cells, the matrix being arranged in rows and columns of cells, and a plurality of control lines. Each cell is coupled to a number of control lines allowing to select and read/write said cell. At least one of said control lines is coupled to cells of a plurality of columns and of at least two rows of the matrix.

Abstract translation: 半导体阵列包括单元矩阵，矩阵以单元格的行和列排列，以及多个控制线。 每个单元耦合到许多控制线，允许选择和读取/写入所述单元。 所述控制线中的至少一个耦合到多个列和至少两行矩阵的单元。

公开(公告)号：US20140225201A1

公开(公告)日：2014-08-14

申请号：US13766228

申请日：2013-02-13

Applicant: Bipul C. PAUL ,  Anurag Mittal ,  Pierre Malinge

Inventor： Bipul C. PAUL ,  Anurag Mittal ,  Pierre Malinge

IPC: G11C11/412 ,  H01L29/66 ,  G06F17/50

CPC classification number: G11C11/412 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/1104

Abstract: Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second NW regions on a substrate; providing first and second RX regions on the first and second NW regions, respectively; providing a contact on the substrate connecting the first and second RX regions; and providing a dummy PC on the substrate connecting the first and second RX regions. Other embodiments include: determining an RX region of an IC design; determining a PPLUS mask region extending along a horizontal direction and being on an entire upper surface of the RX region; determining a NW region extending along a vertical direction and separated from the RX region; and comparing an area of an overlap of the NW region and PPLUS mask region to a threshold value.

Abstract translation: 公开了能够减少边缘和带单元尺寸的方法以及所得到的装置。 实施例包括：在衬底上提供第一和第二NW区域; 分别在第一和第二NW区域上提供第一和第二RX区域; 在连接第一和第二RX区域的基板上提供接触; 以及在连接第一和第二RX区域的基板上提供虚拟PC。 其他实施例包括：确定IC设计的RX区域; 确定沿着水平方向延伸并位于RX区域的整个上表面上的PPLUS掩模区域; 确定沿着垂直方向延伸并与所述RX区分离的NW区域; 以及将NW区域和PPLUS掩模区域的重叠区域与阈值进行比较。

公开(公告)号：US20060261390A1

公开(公告)日：2006-11-23

申请号：US11398855

申请日：2006-04-06

Applicant: Pierre Malinge

Inventor： Pierre Malinge

IPC: H01L29/94

CPC classification number: H01L27/108 ,  H01L27/0207 ,  H01L27/10873 ,  H01L29/4238 ,  H01L29/7881

Abstract: A dynamic random access memory integrated element includes a transistor and a region for the storage of electrical charges. The surface area of an electrical junction between a source region of the transistor and the storage region is smaller than the surface area of an electrical junction between a drain region of the transistor and the storage region. Such a memory element can be fabricated from a standard substrate using SOI technology or from a bulk silicon substrate, and a bit stored in the element can be erased with reduced power consumption.

Abstract translation: 动态随机存取存储器集成元件包括晶体管和用于存储电荷的区域。 晶体管的源极区域和存储区域之间的电连接的表面积小于晶体管的漏极区域和存储区域之间的电连接的表面积。 这样的存储元件可以由使用SOI技术的标准衬底或从体硅衬底制造，并且可以以降低的功耗消除存储在元件中的位。

公开(公告)号：US20130170275A1

公开(公告)日：2013-07-04

申请号：US13591663

申请日：2012-08-22

Applicant: Shishir Kumar ,  Dibya Dipti ,  Pierre Malinge

Inventor： Shishir Kumar ,  Dibya Dipti ,  Pierre Malinge

IPC: G11C5/06

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active are that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that form the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract translation: 双端口SRAM有两个数据存储节点，一个真实的数据和补充数据。 第一下拉晶体管具有形成第一晶体管的漏极区域和与存储器单元的所有其它晶体管有源区域物理隔离的真实数据存储节点的有源。 第二下拉晶体管具有形成第二晶体管的漏极区域的有源区域，该第二晶体管是与存储器单元的所有其它晶体管有源区域物理隔离的互补数据节点。

公开(公告)号：US08183639B2

公开(公告)日：2012-05-22

申请号：US12899663

申请日：2010-10-07

Applicant: Pierre Malinge ,  Jack M. Higman ,  Sanjay R. Parihar

Inventor： Pierre Malinge ,  Jack M. Higman ,  Sanjay R. Parihar

IPC: H01L21/70

CPC classification number: H01L27/11 ,  G11C8/16 ,  G11C11/412 ,  G11C11/413 ,  H01L27/1104 ,  H01L29/4238 ,  Y10S257/903

Abstract: A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node; a first pass transistor coupled to the true data node, and a second pass transistor coupled to the complementary data node. A second active region has the same size and shape as the first active region and has a third pull-down transistor coupled in parallel to the first-pull down transistor, a fourth pull-down transistor coupled in parallel to the second pull-down transistor; a third pass transistor coupled to the true data node, and a fourth pass transistor coupled to the complementary data node. A first pull-up transistor and a second pull-up transistor are located between the first and second active regions.

Abstract translation: 双端口静态随机存取存储单元具有下拉晶体管，上拉晶体管和传输晶体管。 第一有源区具有耦合到真实数据节点的第一下拉晶体管，耦合到互补数据节点的第二下拉晶体管; 耦合到真实数据节点的第一传输晶体管和耦合到互补数据节点的第二传输晶体管。 第二有源区具有与第一有源区相同的尺寸和形状，并且具有与第一下拉晶体管并联耦合的第三下拉晶体管，与第二下拉晶体管并联耦合的第四下拉晶体管 ; 耦合到真实数据节点的第三传输晶体管，以及耦合到互补数据节点的第四传输晶体管。 第一上拉晶体管和第二上拉晶体管位于第一和第二有源区之间。

公开(公告)号：US07428175B2

公开(公告)日：2008-09-23

申请号：US11636315

申请日：2006-12-08

Applicant: Pierre Malinge ,  Rossella Ranica

Inventor： Pierre Malinge ,  Rossella Ranica

IPC: G11C7/10

CPC classification number: G11C11/404 ,  G11C2211/4016

Abstract: A dynamic random access memory (DRAM) including memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belonging to a determined (i.e. selected) row and to a determined (i.e. selected) column, wherein the write circuitry comprises circuitry capable of bringing the drains of the memory cells of the determined column to a voltage V1; circuitry capable of bringing the sources of the memory cells of the determined row to a voltage V2; and circuitry capable of bringing the drains of the memory cells of the columns other than the determined column and the sources of the memory cells of the rows other than the determined row to a voltage V3, voltages V1, V2, and V3 being such that |V1−V2|>|V3−V2| and (V1−V2)×(V3−V2)>0.

Abstract translation: 一种包括以行和列分布的存储单元的动态随机存取存储器（DRAM），每个存储单元包括具有浮动体的MOS晶体管，所述存储器包括用于将数据写入到属于 确定（即选择）行和确定（即选择的）列，其中写电路包括能够将确定的列的存储器单元的漏极导入电压V 1的电路; 能够将确定的行的存储单元的源极电压V 2的电路; 以及能够将列除了所确定的列之外的列的存储单元的漏极和除了所确定的行之外的行的存储单元的源的漏极电压V 3， SUB> 1，V 2和V 3 3使得| V 1 -V 2 ... / SUB > |> | V 3 3 2 和（V 1 -Z 2 -V 2）x（V 3 -V 2）2。

公开(公告)号：US09006841B2

公开(公告)日：2015-04-14

申请号：US13591663

申请日：2012-08-22

Applicant: Shishir Kumar ,  Dibya Dipti ,  Pierre Malinge

Inventor： Shishir Kumar ,  Dibya Dipti ,  Pierre Malinge

IPC: H01L27/11

CPC classification number: H01L27/1104 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/11

Abstract: A dual port SRAM has two data storage nodes, a true data and complementary data. A first pull down transistor has an active area that forms the drain region of the first transistor and the true data storage node that is physically isolated from all other transistor active areas of the memory cell. A second pull down transistor has an active area that forms the drain region of a second transistor that is the complementary data node that is physically isolated from all other transistor active areas of the memory cell.

Abstract translation: 双端口SRAM有两个数据存储节点，一个真实的数据和补充数据。 第一下拉晶体管具有形成第一晶体管的漏极区域和与存储器单元的所有其它晶体管有源区域物理隔离的真实数据存储节点的有源区域。 第二下拉晶体管具有形成第二晶体管的漏极区域的有源区域，该第二晶体管是与存储器单元的所有其它晶体管有源区域物理隔离的互补数据节点。

公开(公告)号：US08921179B2

公开(公告)日：2014-12-30

申请号：US13766228

申请日：2013-02-13

Applicant: Bipul C. Paul ,  Anurag Mittal ,  Pierre Malinge

Inventor： Bipul C. Paul ,  Anurag Mittal ,  Pierre Malinge

IPC: H01L21/8238 ,  G11C11/412 ,  G06F17/50 ,  H01L27/02 ,  H01L27/11

CPC classification number: G11C11/412 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/1104

Abstract: Methodology enabling a reduction of edge and strap cell size, and the resulting device are disclosed. Embodiments include: providing first and second NW regions on a substrate; providing first and second RX regions on the first and second NW regions, respectively; providing a contact on the substrate connecting the first and second RX regions; and providing a dummy PC on the substrate connecting the first and second RX regions. Other embodiments include: determining an RX region of an IC design; determining a PPLUS mask region extending along a horizontal direction and being on an entire upper surface of the RX region; determining a NW region extending along a vertical direction and separated from the RX region; and comparing an area of an overlap of the NW region and PPLUS mask region to a threshold value.

Abstract translation: 公开了能够减少边缘和带单元尺寸的方法以及所得到的装置。 实施例包括：在衬底上提供第一和第二NW区域; 分别在第一和第二NW区域上提供第一和第二RX区域; 在连接第一和第二RX区域的基板上提供接触; 以及在连接第一和第二RX区域的基板上提供虚拟PC。 其他实施例包括：确定IC设计的RX区域; 确定沿着水平方向延伸并位于RX区域的整个上表面上的PPLUS掩模区域; 确定沿着垂直方向延伸并与所述RX区分离的NW区域; 以及将NW区域和PPLUS掩模区域的重叠区域与阈值进行比较。

公开(公告)号：US20070133309A1

公开(公告)日：2007-06-14

申请号：US11636315

申请日：2006-12-08

Applicant: Pierre Malinge ,  Rossella Ranica

Inventor： Pierre Malinge ,  Rossella Ranica

IPC: G11C7/10

CPC classification number: G11C11/404 ,  G11C2211/4016

Abstract: A dynamic random access memory (DRAM) comprising memory cells distributed in rows and in columns, each memory cell comprising a MOS transistor with a floating body, the memory comprising circuitry for writing a datum into a determined (i.e. selected) memory cell belonging to a determined (i.e. selected) row and to a determined (i.e. selected) column, wherein the write circuitry comprises circuitry capable of bringing the drains of the memory cells of the determined column to a voltage V1; circuitry capable of bringing the sources of the memory cells of the determined row to a voltage V2; and circuitry capable of bringing the drains of the memory cells of the columns other than the determined column and the sources of the memory cells of the rows other than the determined row to a voltage V3, voltages V1, V2, and V3 being such that |V1−V2|>|V3−V2| and (V1−V2)×(V3−V2)>0.

Abstract translation: 一种动态随机存取存储器（DRAM），包括以行和列分布的存储器单元，每个存储器单元包括具有浮动体的MOS晶体管，所述存储器包括用于将数据写入到属于 确定（即选择）行和确定（即选择的）列，其中写电路包括能够将确定的列的存储器单元的漏极导入电压V 1的电路; 能够将确定的行的存储单元的源极电压V 2的电路; 以及能够将列除了所确定的列之外的列的存储单元的漏极和除了所确定的行之外的行的存储单元的源的漏极电压V 3的电路，电压V < SUB> 1，V 2和V 3 3使得| V 1 -V 2 ... / SUB > |> | V 3 3 2 和（V 1 -Z 2 -V 2）x（V 3 -V 2）2。