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1.发明授权Parallel voltage regulators with different operating characteristics collectively forming a single regulator with wide operating range 失效具有不同工作特性的并联稳压器共同形成了具有宽工作范围的单个稳压器
公开(公告)号：US4611162A
公开(公告)日：1986-09-09
申请号：US620047
申请日：1984-06-12
申请人： Pietro Erratico , Pietro Menniti
发明人： Pietro Erratico , Pietro Menniti
CPC分类号： G05F1/59 , Y10T307/675
摘要： A monolithic integrated voltage regulator consists of a multiplicity of regulator circuits connected in parallel to one another. These circuits have different dropouts and the voltage established across each set of output terminals is held at a predetermined constant value by means of a regulator circuit having its feedback circuits connected thereto. The predetermined value of the voltage across one set of output terminals is deliberately selected to be more or less elevated according to whether the dropout of its associated regulator circuit is more or less elevated.
摘要翻译： 单片集成稳压器由多个彼此并联连接的调节器电路组成。 这些电路具有不同的压差，并且通过其反馈电路与其连接的调节器电路将建立在每组输出端子上的电压保持在预定的恒定值。 一组输出端子上的电压的预定值根据其相关联的调节器电路的压差是或多或少升高被故意选择为或多或少地升高。
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公开(公告)号：US5401995A
公开(公告)日：1995-03-28
申请号：US99854
申请日：1993-07-30
申请人： Ferdinando Lari , Pietro Erratico
发明人： Ferdinando Lari , Pietro Erratico
CPC分类号： H03F1/3211
摘要： An operational amplifier, of a type which comprises a differential cell transconductor input stage (2) incorporating a current mirror (5) provided with a pair of degenerative resistors (R9,R10) and a gain stage (7), driven directly by a transistor (Q12) of said mirror (5), has each degenerative resistor (R9,R10) formed within an epitaxial well wherewith a parasitic diode (D1,D2) is associated. Each diode (D1,D2) is connected in parallel with its corresponding resistor (R9,R10) to prevent the transistor (Q12) which drives the gain stage (7) from becoming saturated.
摘要翻译： 一种运算放大器，它是一种类型的运算放大器，它包括一个包含电流镜（5）的差分单元跨导体输入级（2），该电流反射镜（5）设有一对由晶体管直接驱动的退化电阻（R9，R10）和增益级（7） （5）的（Q12）具有形成在外延阱内的每个退化电阻器（R9，R10），其中寄生二极管（D1，D2）相关联。 每个二极管（D1，D2）与其对应的电阻器（R9，R10）并联连接，以防止驱动增益级（7）的晶体管（Q12）变得饱和。
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公开(公告)号：US5231051A
公开(公告)日：1993-07-27
申请号：US769600
申请日：1991-10-01
申请人： Livio Baldi , Pietro Erratico
发明人： Livio Baldi , Pietro Erratico
IPC分类号： H01L21/28 , H01L21/285 , H01L21/302 , H01L21/3065 , H01L21/768
CPC分类号： H01L21/76879 , H01L21/7684 , Y10S438/963 , Y10S438/976
摘要： An improved planarity when forming contact plugs by a blanket CVD deposition of a metallic matrix layer followed by etchback is achieved by performing a first etchback step to expose the surface of the dielectric material underlying the filling metal layer, while masking the top of the metal plugs with resist caps. The resist caps are formed using a mask derived by field inversion and enlargement from the actual contact mask used for defining the contact areas. With the resist caps covering the contact plugs, the filling metallic material is overetched to eliminate residues along with discontinuities from the planarity of the surface, while shielding the top of the plugs from the overetch. The masked overetch is preferably conducted under conditions of reduced anisotropy and increased selectivity in respect to the first etchback step.
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4.发明授权公开(公告)号：US06693039B2
公开(公告)日：2004-02-17
申请号：US09797206
申请日：2001-02-27
IPC分类号： H01L21302
CPC分类号： B81C1/00404
摘要： The process comprises the steps of forming, on top of a semiconductor material wafer, a holed mask having a lattice structure and comprising a plurality of openings each having a substantially square shape and a side with an inclination of 45° with respect to the flat of the wafer; carrying out an anisotropic etch in TMAH of the wafer, using said holed mask, thus forming a cavity, the cross section of which has the shape of an upside-down isosceles trapezium; and carrying out a chemical vapor deposition using TEOS, thus forming a TEOS layer which completely closes the openings of the holed mask and defines a diaphragm overlying the cavity and on which a suspended integrated structure can subsequently be manufactured.
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公开(公告)号：US4716321A
公开(公告)日：1987-12-29
申请号：US827921
申请日：1986-02-10
申请人： Pietro Erratico
发明人： Pietro Erratico
摘要： A low noise, high thermal stability attenuator of the integratable type is disclosed. The attenuator comprises a fixed network of resistive elements, having a plurality of outputs each at a different attenuation level, and a switched amplifier receiving at its input such different attenuation outputs, as well as a control signal which specifies which of the amplifier inputs is to be output. Advantageously, this attenuator may be implemented in several stages, each having different attenuation ranges or steps.
摘要翻译： 公开了一种可集成型的低噪声，高热稳定性衰减器。 衰减器包括电阻元件的固定网络，其具有各自具有不同衰减电平的多个输出，以及开关放大器，其输入端接收不同的衰减输出，以及控制信号，该控制信号指定哪个放大器输入为 输出。 有利地，该衰减器可以分几个阶段实现，每个阶段具有不同的衰减范围或步骤。
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公开(公告)号：US5525832A
公开(公告)日：1996-06-11
申请号：US17816
申请日：1993-02-16
申请人： Pietro Consiglio , Pietro Erratico
发明人： Pietro Consiglio , Pietro Erratico
CPC分类号： H01L27/0251
摘要： A substrate insulation device includes power supply terminals which are connected to a terminal of an active integrated element which has, with respect to a substrate on which it is defined, at least one reverse-biased junction.
摘要翻译： 基板绝缘装置包括电源端子，其连接到有源集成元件的端子，该有源集成元件相对于限定了该基板的基板，具有至少一个反向偏置接合部。
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7.发明授权Monolithically integratable high-efficiency control circuit for switching transistors 失效用于开关晶体管的单片可积分高效率控制电路
公开(公告)号：US4698519A
公开(公告)日：1987-10-06
申请号：US812935
申请日：1985-12-23
申请人： Carlo Cini , Claudio Diazzi , Pietro Erratico
发明人： Carlo Cini , Claudio Diazzi , Pietro Erratico
IPC分类号： H03K17/0412 , H03K17/66 , H03K17/60 , H03K3/33
CPC分类号： H03K17/04126 , H03K17/665
摘要： A monolithically integrable high-efficiency control circuit for the switching of transistors includes a first transistor whose base terminal is connected to a source of switching signals. A second transistor whose base is connected to a current generator, drives a third transistor which connected in series with the first transistor such that the first and third transistors are connected between two terminals of a supply voltage generator. The emitter terminal of the third transistor forms an output terminal of the control circuit and is connected to the collector terminal of the first transistor by means of a parallel connected diode and a resistor combination. The circuit also includes a fourth transistor, whose base terminal is connected through a resistor to the base terminal of the third transistor and whose collector and emitter terminals are respectively connected to the base terminal of the second transistor and to the collector terminal of the first transistor.
摘要翻译： 用于晶体管开关的单片可积分高效率控制电路包括其基极连接到开关信号源的第一晶体管。 基极连接到电流发生器的第二晶体管驱动与第一晶体管串联连接的第三晶体管，使得第一和第三晶体管连接在电源电压发生器的两个端子之间。 第三晶体管的发射极端子形成控制电路的输出端，并通过并联二极管和电阻器组合连接到第一晶体管的集电极端子。 电路还包括第四晶体管，其基极端子通过电阻器连接到第三晶体管的基极端子，其集电极和发射极端子分别连接到第二晶体管的基极端子和第一晶体管的集电极端子 。
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公开(公告)号：US06400001B1
公开(公告)日：2002-06-04
申请号：US09493842
申请日：2000-01-28
申请人： Stefano Manzini , Pietro Erratico
发明人： Stefano Manzini , Pietro Erratico
IPC分类号： H01L2993
CPC分类号： H01L29/94
摘要： A varactor has a gate region, first and second biasing regions of N+ type embedded in a well, and first and second extraction regions of P+ type, forming a pair of PN junctions with the well. The PN junctions are inversely biased and extract charge accumulating in the well, below the gate region, when the gate region is biased to a lower voltage than a predetermined threshold value.
摘要翻译： 变容二极管具有栅极区域，嵌入阱中的N +型的第一和第二偏置区域以及P +型的第一和第二提取区域，与阱形成一对PN结。 当栅极区域被偏置到比预定阈值更低的电压时，PN结反向偏置并提取在阱中的阱下面积聚的电荷。
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9.发明授权
公开(公告)号：US5448636A
公开(公告)日：1995-09-05
申请号：US017789
申请日：1993-02-16
摘要： Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.
摘要翻译： 用于限制电话机械开关的工作电压的装置包括用于连接到电话线的端子，用于从第一端子延伸的控制电路的连接和电源分支，该分支具有第一开关，第一齐纳二极管的阴极端子 二极管和第一MOSFET晶体管的源极端子连接到第一开关的输出端子，第一MOSFET晶体管的栅极端子通过齐纳二极管的阳极端子连接到第一端子。 可以调节由装置吸收的电流。
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10.发明授权Control circuit with compensation of the anode voltage variation for televisor vertical deflection stage 失效控制电路补偿电视机垂直偏转阶段的阳极电压变化
公开(公告)号：US4752722A
公开(公告)日：1988-06-21
申请号：US836116
申请日：1986-03-04
申请人： Pietro Erratico , Mauro Merlo , Silvano Coccetti
发明人： Pietro Erratico , Mauro Merlo , Silvano Coccetti
CPC分类号： H04N3/16
摘要： An amplifier stage with variable gain dependent on the anode voltage is interposed between a ramp generator having constant amplitude ramp output voltage and the vertical deflection stage in such a manner as to vary the input voltage of said vertical deflection stage in accordance with anode voltage variations. In such a manner the vertical deflection current varies correspondingly.
摘要翻译： 具有取决于阳极电压的可变增益的放大器级介于具有恒定幅度斜坡输出电压的斜坡发生器和垂直偏转级之间，以便根据阳极电压变化改变所述垂直偏转级的输入电压。 以这种方式，垂直偏转电流相应地变化。
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