公开(公告)号：US06787882B2

公开(公告)日：2004-09-07

申请号：US10261586

申请日：2002-10-02

Applicant: Steven Kirchoefer

Inventor： Steven Kirchoefer

IPC: H01L2993

CPC classification number: H01L29/93 ,  H01L29/155

Abstract: A semiconductor device includes a plurality of barrier layers and a plurality of quantum well layers which are alternately interleaved with each other and disposed on a substrate of semiconductor material so as to form a multiple-heterojunction varactor diode. The barrier layers and quantum well layers are doped with impurities. The varactor diode includes an ohmic contact which is electrically connected to a heavily doped embedded region and a Schottky contact which is electrically connected to a depletion region of the diode. The ohmic contact and the Schottky contact enable an external voltage source to be applied to the contacts so as to provide a bias voltage to the varactor diode. A variable capacitance is produced as a result of the depletion region varying with a variation in the bias voltage. The varactor diode also provides a constant series resistance.

Abstract translation: 半导体器件包括多个势垒层和多个量子阱层，它们彼此交替交替并且设置在半导体材料的衬底上，以便形成多异质结变容二极管。 阻挡层和量子阱层掺杂有杂质。 变容二极管包括电连接到重掺杂的嵌入区域的欧姆接触和电连接到二极管的耗尽区的肖特基接触。 欧姆接触和肖特基接触使得能够将外部电压源施加到触点，以便向变容二极管提供偏置电压。 由于耗尽区域随着偏置电压的变化而变化，产生可变电容。 变容二极管还提供恒定的串联电阻。

公开(公告)号：US06316819B1

公开(公告)日：2001-11-13

申请号：US09101520

申请日：1998-11-13

Applicant: Zoran Zivic

Inventor： Zoran Zivic

IPC: H01L2993

CPC classification number: H01L29/93 ,  H01L29/22

Abstract: A multilayer ZnO polycrystalline diode that protects against electrostatic discharges, over-current, and voltage surges is provided. The polycrystalline diode includes a block having a plurality of polycrystalline layers in parallel having a first lateral side and a second lateral side. A polycrystalline system is formed by a network of the ZnO diodes. Each diode further includes a plurality of inner electrodes, wherein each inner electrode includes metal and is placed among the plurality of parallel polycrystalline layers, and wherein one end of each inner electrode is placed to alternately terminate at one of the first lateral side and the second lateral side of the block, and wherein the remainder of each inner electrode is surrounded by the parallel polycrystalline layers. A pair of outer electrodes, each including metal and covering each of the first lateral side and the second lateral side of the block are also provided.

Abstract translation: 提供了一种防止静电放电，过电流和电压浪涌的多层ZnO多晶二极管。 多晶二极管包括具有平行的多个多晶层的块，其具有第一侧面和第二侧面。 多晶体系由ZnO二极管的网络形成。 每个二极管还包括多个内部电极，其中每个内部电极包括金属并且放置在多个平行多晶层之间，并且其中每个内部电极的一端被置于交替地终止于第一侧面和第二侧面中的一个 并且其中每个内部电极的其余部分被平行的多晶层围绕。 还提供一对外电极，每个外电极包括金属并覆盖块的第一侧面和第二横向侧。

公开(公告)号：US06825546B1

公开(公告)日：2004-11-30

申请号：US10035346

申请日：2001-12-28

Applicant: John Q. Walker ,  Todd A. Randazzo

Inventor： John Q. Walker ,  Todd A. Randazzo

IPC: H01L2993

CPC classification number: H01L29/93

Abstract: A varactor is formed with a semiconductor junction having a retrograde dopant concentration profile in a depletion region. The retrograde dopant concentration profile results in an approximately linear capacitance/voltage characteristic response of the varactor. The retrograde dopant concentration profile also enables a peak of the dopant concentration to function as a low resistance conductive path connecting to the varactor.

Abstract translation: 在耗尽区中形成具有逆向掺杂剂浓度分布的半导体结的变容二极管。 逆向掺杂剂浓度分布导致变容二极管的近似线性电容/电压特性响应。 逆向掺杂剂浓度分布还使得掺杂剂浓度的峰值能够用作连接到变容二极管的低电阻导电路径。

公开(公告)号：US06686640B2

公开(公告)日：2004-02-03

申请号：US10044107

申请日：2002-01-11

Applicant: Bongki Mheen ,  Dongwoo Suh ,  Jin-Yeong Kang

Inventor： Bongki Mheen ,  Dongwoo Suh ,  Jin-Yeong Kang

IPC: H01L2993

CPC classification number: H01L29/66174 ,  H01L29/66242 ,  H01L29/93

Abstract: A varactor includes a semiconductor substrate of a first conductivity type, a high-concentration buried collector region of a second conductivity type formed in an upper portion of the semiconductor substrate, a collector region of the second conductivity type formed on a first surface of the high-concentration buried collector region, a high-concentration collector contact region of the second conductivity type formed on a second surface of the high-concentration buried collector region, a high-concentration silicon-germanium base region of the first conductivity type formed on the collector region, a metal silicide layer formed on the silicon-germanium base region, a first electrode layer formed to contact the metal silicide layer, and a second electrode layer formed to be electrically connected to the collector contact region.

Abstract translation: 变容二极管包括第一导电类型的半导体衬底，形成在半导体衬底的上部的第二导电类型的高浓度集电区，在第一表面上形成第二导电类型的集电极区 浓度埋集电极区域，形成在高浓度埋集体区域的第二表面上的第二导电类型的高浓度集电极接触区域，形成在集电体上的第一导电类型的高浓度硅 - 锗基区域 形成在硅 - 锗基区上的金属硅化物层，形成为与金属硅化物层接触的第一电极层和形成为与集电极接触区电连接的第二电极层。

公开(公告)号：US06667539B2

公开(公告)日：2003-12-23

申请号：US09683014

申请日：2001-11-08

Applicant: Eric Adler

Inventor： Eric Adler

IPC: H01L2993

CPC classification number: H01L29/94

Abstract: A varactor circuit having an increased tuning range comprises a first varactor in series with a second varactor between first and second terminals. A resistor is connected between the first and second terminals. A tap of the resistor is connected to a junction of the first and second varactors. This circuit effectively doubles tuning range compared to a single varactor.

公开(公告)号：US06717238B2

公开(公告)日：2004-04-06

申请号：US09818449

申请日：2001-03-27

Applicant: Ming-Dou Ker ,  Hsin-Chin Jiang

Inventor： Ming-Dou Ker ,  Hsin-Chin Jiang

IPC: H01L2993

CPC classification number: H01L24/05 ,  H01L23/5222 ,  H01L24/48 ,  H01L2224/02122 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05012 ,  H01L2224/05093 ,  H01L2224/05095 ,  H01L2224/05096 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05567 ,  H01L2224/05599 ,  H01L2224/48463 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A low-capacitance bonding pad for a semiconductor device. A diffusion region is formed in a substrate, and a bonding pad is formed on the substrate and aligned with the diffusion region. The bonding pad is made from a stacked metal layer and a metal layer. The stacked metal layer is made from a plurality of metal layers and a plurality of dielectric layers, and the metal layers and the dielectric layers are stacked alternately. The metal layers stacked in the stacked metal layer are formed with small areas. Each of the metal layers stacked in the stacked metal layer is coupled with the adjacent metal layer by via plugs.

Abstract translation: 一种用于半导体器件的低电容焊盘。 在衬底中形成扩散区，并且在衬底上形成接合焊盘并与扩散区对准。 接合焊盘由堆叠的金属层和金属层制成。 堆叠的金属层由多个金属层和多个电介质层制成，并且金属层和电介质层交替堆叠。 堆叠在层叠金属层中的金属层形成有小面积。 堆叠在堆叠金属层中的每个金属层通过插塞与相邻的金属层耦合。

公开(公告)号：US06661074B2

公开(公告)日：2003-12-09

申请号：US10070122

申请日：2002-03-01

Applicant: Bernhard Bollig ,  Hans Martin Ritter

Inventor： Bernhard Bollig ,  Hans Martin Ritter

IPC: H01L2993

CPC classification number: H01L27/0808 ,  H01L27/0682 ,  H01L27/0802

Abstract: A receiver for radio or television signals provided with a high-frequency circuit having a discrete semiconductor component which includes a planar variable capacitance diode and an integrated series resistor formed on a common semiconductor or substrate. The receiver has lower parasitic capacitance and improved data reception, resulting in an increase of the Q factor of the variable capacitance diode and an increase in the circuit performance. The overall circuit loss is also reduced.

Abstract translation: 一种用于无线电或电视信号的接收机，其具有具有分立半导体部件的高频电路，该分立半导体部件包括形成在公共半导体或基板上的平面可变电容二极管和集成串联电阻器。 接收器具有较低的寄生电容和改进的数据接收，导致可变电容二极管的Q因数的增加和电路性能的增加。 总体电路损耗也降低。

公开(公告)号：US06642607B2

公开(公告)日：2003-11-04

申请号：US10061365

申请日：2002-02-04

Applicant: Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

Inventor： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

IPC: H01L2993

CPC classification number: H01L29/93 ,  H01L27/0664 ,  H01L27/0808

Abstract: A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

Abstract translation: 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。

公开(公告)号：US06400001B1

公开(公告)日：2002-06-04

申请号：US09493842

申请日：2000-01-28

Applicant: Stefano Manzini ,  Pietro Erratico

Inventor： Stefano Manzini ,  Pietro Erratico

IPC: H01L2993

CPC classification number: H01L29/94

Abstract: A varactor has a gate region, first and second biasing regions of N+ type embedded in a well, and first and second extraction regions of P+ type, forming a pair of PN junctions with the well. The PN junctions are inversely biased and extract charge accumulating in the well, below the gate region, when the gate region is biased to a lower voltage than a predetermined threshold value.

Abstract translation: 变容二极管具有栅极区域，嵌入阱中的N +型的第一和第二偏置区域以及P +型的第一和第二提取区域，与阱形成一对PN结。 当栅极区域被偏置到比预定阈值更低的电压时，PN结反向偏置并提取在阱中的阱下面积聚的电荷。

公开(公告)号：US06762482B2

公开(公告)日：2004-07-13

申请号：US10336956

申请日：2003-01-06

Applicant: Wen-Chung Liu ,  Bor-Ru Sheu ,  Yoshiaki Fukuzumi

Inventor： Wen-Chung Liu ,  Bor-Ru Sheu ,  Yoshiaki Fukuzumi

IPC: H01L2993

CPC classification number: H01L21/7687 ,  H01L21/3212 ,  H01L21/76828 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76877 ,  H01L28/60 ,  H01L28/90

Abstract: A memory device with composite contact plug and method for manufacturing the same. The composite contact plug comprises a first insulating layer deposited on a semiconductor substrate. A contact hole is formed to penetrate through the first insulation layer. A barrier layer is deposited in the contact hole and fills a portion of the contact hole. A contact plug is formed on the barrier layer and fills the contact hole. The first insulating layer is etched back until the surface of the first insulating layer is below the contact plug. A diffusion barrier layer is then deposited on the first insulating layer and the contact plug. The diffusion barrier layer is planarized until the contact plug is exposed to form a composite contact plug. The memory device is constructed on the composite contact plug.

Abstract translation: 具有复合接触插头的记忆装置及其制造方法。 复合接触插塞包括沉积在半导体衬底上的第一绝缘层。 形成穿过第一绝缘层的接触孔。 阻挡层沉积在接触孔中并填充接触孔的一部分。 接触塞形成在阻挡层上并填充接触孔。 第一绝缘层被回蚀刻直到第一绝缘层的表面在接触插塞之下。 然后在第一绝缘层和接触插塞上沉积扩散阻挡层。 扩散阻挡层被平坦化，直到接触塞被暴露以形成复合接触塞。 存储器件构造在复合接触插头上。