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    MAGNETORESISTIVE ELEMENT HAVING AN ADJACENT-BIAS LAYER AND A TOGGLE WRITING SCHEME
    2.
    发明申请
    MAGNETORESISTIVE ELEMENT HAVING AN ADJACENT-BIAS LAYER AND A TOGGLE WRITING SCHEME 有权

    公开(公告)号：US20220278270A1

    公开(公告)日：2022-09-01

    申请号：US17187864

    申请日：2021-02-28

    申请人： Yimin Guo ,  Rongfu Xiao ,  Jun Chen

    发明人： Yimin Guo ,  Rongfu Xiao ,  Jun Chen

    IPC分类号： H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  G11C11/16

    摘要： A magnetoresistive element using combined spin-transfer-torque controlled magnetic bias and VCMA effects comprising a free layer and an adjacent-bias layer separated by a nonmagnetic spacing layer, wherein the free layer has an interfacial perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface, the adjacent-bias layer has a perpendicular magnetic anisotropy and a variable magnetization direction substantially perpendicular to a film surface, and the perpendicular anisotropy of the free layer is sufficiently higher than that of the adjacent-bias layer such that the critical switching current to reverse the free layer magnetization direction is at least 3 times as high as the critical switching current to reverse the adjacent-bias layer magnetization direction. Further, there is provided a toggle writing method of the perpendicular magnetoresistive element comprises: applying a first write pulse having a first voltage magnitude and a first pulse width to reverse the adjacent-bias layer magnetization direction to be anti-parallel to the free layer magnetization direction by spin-transfer-torque effect, and applying a second write pulse having a second voltage magnitude and a second pulse width to reverse the free layer magnetization direction to be parallel to the adjacent-bias layer magnetization direction by voltage-controlled magnetic anisotropy effect under the magnetic dipole bias field from the adjacent-bias layer.

    Lattice matched seed layer to improve PMA for perpendicular magnetic pinning
    3.
    发明授权
    Lattice matched seed layer to improve PMA for perpendicular magnetic pinning 有权

    公开(公告)号：US11088200B1

    公开(公告)日：2021-08-10

    申请号：US16786304

    申请日：2020-02-10

    申请人： Rongfu Xiao

    发明人： Rongfu Xiao

    IPC分类号： G11C11/16 ,  H01L27/22 ,  H01L43/02 ,  H01F10/32 ,  H01L43/10

    摘要： The invention comprises a novel composite seed layer with lattice-matched crystalline structure so that an excellent epitaxial growth of magnetic pinning layer along its FCC (111) orientation can be achieved, resulting in a significant enhancement of PMA for perpendicular spin-transfer-torque magnetic-random-access memory (pSTT-MRAM) using perpendicular magnetoresistive elements as basic memory cells which potentially replace the conventional semiconductor memory used in electronic chips, especially mobile chips for power saving and non-volatility.

    METHOD FOR MAKINGA MAGNETIC RANDOM ACCESS MEMORY ELEMENT WITH SMALL DIMENSION AND HIGH QULITY
    4.
    发明申请
    METHOD FOR MAKINGA MAGNETIC RANDOM ACCESS MEMORY ELEMENT WITH SMALL DIMENSION AND HIGH QULITY 审中-公开
    制造具有小尺寸和高数量的磁性随机存取元件的方法

    公开(公告)号：US20160163970A1

    公开(公告)日：2016-06-09

    申请号：US14562660

    申请日：2014-12-05

    申请人： Rongfu Xiao

    发明人： Rongfu Xiao

    IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L43/02

    CPC分类号： H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

    摘要： This invention is about a method to make an MRAM element with small dimension, by building an MTJ as close as possible to an associated via connecting an associated circuitry in a semiconductor wafer. The invention provides a process scheme to flatten the interface of bottom electrode during film deposition, which ensures a good deposition of atomically smooth MTJ multilayer as close as possible to an associated via which otherwise might be atomically rough. The flattening scheme is first to deposit a thin amorphous conducting layer in the middle of BE deposition and immediately to bombard the amorphous layer by low energy ions to provide kinetic energy for surface atom diffusion to move from high point to low kinks. With such surface flattening scheme, not only the MRAM element can be made extremely small, but its device performance and magnetic stability can also be greatly improved.

    摘要翻译： 本发明涉及一种制造具有小尺寸的MRAM元件的方法，通过构建尽可能靠近连接半导体晶片中的相关电路的相关联的通孔的MTJ。 本发明提供了一种在膜沉积期间使底部电极的界面平坦化的工艺方案，其确保了原子光滑的MTJ多层的尽可能接近的可能原子粗糙的相关通孔的良好沉积。 平坦化方案首先在BE沉积的中间沉积薄的非晶导电层，并立即通过低能离子轰击非晶层，以提供动能，使表面原子扩散从高点移动到低扭结。 通过这种表面平坦化方案，不仅可以使MRAM元件非常小，而且可以大大提高其器件性能和磁稳定性。

    High density spin-transfer torque MRAM process
    7.
    发明授权
    High density spin-transfer torque MRAM process 有权
    高密度自旋转移力矩MRAM工艺

    公开(公告)号：US08183061B2

    公开(公告)日：2012-05-22

    申请号：US12931648

    申请日：2011-02-07

    申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

    发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

    IPC分类号： H01L21/441

    CPC分类号： H01L27/228 ,  H01L43/12

    摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.

    摘要翻译： 公开了一种STT-MRAM集成方案，其中通过在CMOS着陆焊盘，接触和覆盖VAC的金属（VAM）焊盘上形成中间通孔接触（VAC）来简化MTJ和CMOS金属之间的连接，以及MTJ 在VAM上。 执行双镶嵌工艺，通过设备区域中的VAC / VAM / MTJ堆叠将BIT线金属连接到CMOS着陆焊盘，并通过设备区域外的BIT连接通孔将BIT线连接焊盘连接到CMOS连接焊盘。 VAM焊盘是由Ta，TaN或用作扩散阻挡层的其它导体制成的单层或复合材料，具有用于MTJ形成的高度光滑的表面，并且在化学机械抛光工艺期间提供了与补充介电材料的优异选择性。 每个VAC为500至3000埃厚，以最小化额外的电路电阻并最小化蚀刻负担。

    Method of magnetic tunneling layer processes for spin-transfer torque MRAM
    8.
    发明授权
    Method of magnetic tunneling layer processes for spin-transfer torque MRAM 有权
    旋转转矩MRAM的磁隧道层工艺方法

    公开(公告)号：US08133745B2

    公开(公告)日：2012-03-13

    申请号：US11975045

    申请日：2007-10-17

    申请人： Tom Zhong ,  Rongfu Xiao ,  Chyu-Jiuh Torng ,  Adam Zhong

    发明人： Tom Zhong ,  Rongfu Xiao ,  Chyu-Jiuh Torng ,  Adam Zhong

    IPC分类号： H01L21/00

    CPC分类号： H01L43/12 ,  B82Y10/00 ,  H01L27/228

    摘要： A method for forming a MTJ in a STT-MRAM is disclosed in which the easy-axis CD is determined independently of the hard-axis CD. One approach involves two photolithography steps and two etch steps to form a post in a hard mask which is transferred through a MTJ stack of layers by a third etch process. Optionally, the third etch may stop on the tunnel barrier or in the free layer. A second embodiment involves forming a first parallel line pattern on a hard mask layer and transferring the line pattern through the MTJ stack with a first etch step. A planar insulation layer is formed adjacent to the sidewalls in the line pattern and then a second parallel line pattern is formed which is transferred by a second etch through the MTJ stack to form a post pattern. Etch end point may be controlled independently for hard-axis and easy-axis dimensions.

    摘要翻译： 公开了一种用于在STT-MRAM中形成MTJ的方法，其中容易轴CD独立于硬轴CD来确定。 一种方法涉及两个光刻步骤和两个蚀刻步骤，以在通过第三蚀刻工艺通过MTJ叠层堆叠的硬掩模中形成柱。 可选地，第三蚀刻可以在隧道势垒上或在自由层中停止。 第二实施例涉及在硬掩模层上形成第一平行线图案，并通过第一蚀刻步骤通过MTJ堆叠传送线图案。 平面绝缘层与线图案中的侧壁相邻地形成，然后形成第二平行线图案，其通过第二次蚀刻通过MTJ叠层转印以形成柱形图案。 蚀刻终点可以独立控制硬轴和易轴尺寸。

    High density spin-transfer torque MRAM process
    9.
    发明申请
    High density spin-transfer torque MRAM process 有权

    公开(公告)号：US20110129946A1

    公开(公告)日：2011-06-02

    申请号：US12931648

    申请日：2011-02-07

    申请人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

    发明人： Tom Zhong ,  Chyu-Jiuh Torng ,  Rongfu Xiao ,  Adam Zhong ,  Wai-Ming Johnson Kan ,  Daniel Liu

    IPC分类号： H01L21/00

    CPC分类号： H01L27/228 ,  H01L43/12

    摘要： A STT-MRAM integration scheme is disclosed wherein the connection between a MTJ and CMOS metal is simplified by forming an intermediate via contact (VAC) on a CMOS landing pad, a metal (VAM) pad that contacts and covers the VAC, and a MTJ on the VAM. A dual damascene process is performed to connect BIT line metal to CMOS landing pads through VAC/VAM/MTJ stacks in a device region, and to connect BIT line connection pads to CMOS connection pads through BIT connection vias outside the device region. The VAM pad is a single layer or composite made of Ta, TaN, or other conductors which serves as a diffusion barrier, has a highly smooth surface for MTJ formation, and provides excellent selectivity with refill dielectric materials during a chemical mechanical polish process. Each VAC is from 500 to 3000 Angstroms thick to minimize additional circuit resistance and minimize etch burden.