公开(公告)号：US07548593B2

公开(公告)日：2009-06-16

申请号：US11228090

申请日：2005-09-15

申请人： Puay Hoe Andrew See ,  Gary John Ballantyne ,  James Jaffee ,  Gurkanwal Kamal Sahota

发明人： Puay Hoe Andrew See ,  Gary John Ballantyne ,  James Jaffee ,  Gurkanwal Kamal Sahota

IPC分类号： H03C3/00

CPC分类号： H04L27/361 ,  H03C3/0966 ,  H03C3/0983

摘要： A phase modulator faithfully reproduces higher frequency modulation using an offset phase-locked loop (OPLL) without passing excessive noise through an increased bandwidth of the OPLL. A quadrature modulator modulates information from a baseband signal onto a passband IF signal and, after a limiter strips away amplitude variations, the OPLL reproduces the phase modulation on an RF signal. The OPLL introduces a group delay that does not vary linearly with the modulation frequency and that consequently causes distortion when uncompensated. A baseband filter filters the amplitude of the baseband signal and introduces a complementary group delay that compensates for the OPLL group delay and results in a combined group delay of the baseband filter, quadrature modulator, limiter and OPLL that remains substantially constant as modulation frequency varies. Compensating for the OPLL group delay reduces distortion and the spectral energy at offset frequencies from the carrier frequency of the RF signal.

摘要翻译： 相位调制器使用偏移锁相环（OPLL）忠实地再现更高的频率调制，而不会通过OPLL的带宽增加而过多的噪声。 正交调制器将信号从基带信号调制到通带IF信号上，并且在限幅器剥离幅度变化之后，OPLL再现RF信号上的相位调制。 OPLL引入了不随调制频率线性变化的群延迟，从而导致无补偿时的失真。 基带滤波器对基带信号的幅度进行滤波，并引入补偿组延迟，补偿OPLL组延迟，并导致基带滤波器，正交调制器，限幅器和OPLL的组合群延迟，其随调制频率变化而保持基本恒定。 补偿OPLL组延迟可以减少偏移频率下的失真和频谱能量与RF信号的载波频率。

公开(公告)号：US07711329B2

公开(公告)日：2010-05-04

申请号：US10792171

申请日：2004-03-02

申请人： Vladimir Aparin ,  Gary John Ballantyne ,  Charles J. Persico

发明人： Vladimir Aparin ,  Gary John Ballantyne ,  Charles J. Persico

IPC分类号： H04B1/44

CPC分类号： H04B1/525

摘要： An adaptive filter suitable for fabrication on an RF integrated circuit and used for transmit (TX) leakage rejection in a wireless full-duplex communication system is described. The adaptive filter includes a summer and an adaptive estimator. The summer receives an input signal having a TX leakage signal and an estimator signal having an estimate of the TX leakage signal, subtracts the estimator signal from the input signal, and provides an output signal having the TX leakage signal attenuated. The adaptive estimator receives the output signal and a reference signal having a version of the transmit signal, estimates the TX leakage signal in the input signal based on the output signal and the reference signal, and provides the estimator signal. The adaptive estimator may utilize an LMS algorithm to minimize a mean square error between the TX leakage signal in the input signal and the TX leakage signal estimate in the estimator signal.

摘要翻译： 描述了适用于在RF集成电路上制造并用于无线全双工通信系统中的发射（TX）泄漏抑制的自适应滤波器。 自适应滤波器包括一个加法器和一个自适应估计器。 夏天接收具有TX泄漏信号的输入信号和具有TX泄漏信号的估计的估计信号，从输入信号中减去估计器信号，并且提供具有衰减的TX泄漏信号的输出信号。 自适应估计器接收输出信号和具有发射信号版本的参考信号，基于输出信号和参考信号估计输入信号中的TX泄漏信号，并提供估计器信号。 自适应估计器可以利用LMS算法来最小化输入信号中的TX泄漏信号与估计器信号中的TX泄漏信号估计之间的均方误差。

公开(公告)号：US20090302963A1

公开(公告)日：2009-12-10

申请号：US12133726

申请日：2008-06-05

申请人： Gary John Ballantyne ,  Arun Jayaraman ,  Bo Sun ,  Gurkanwal Singh Sahota

发明人： Gary John Ballantyne ,  Arun Jayaraman ,  Bo Sun ,  Gurkanwal Singh Sahota

IPC分类号： H03C5/00

CPC分类号： H04L27/362 ,  H03F3/2176

摘要： A bi-polar modulator that can perform quadrature modulation using amplitude modulators is described. In one design, the bi-polar modulator includes first and second amplitude modulators and a summer. The first amplitude modulator amplitude modulates a first carrier signal with a first input signal and provides a first amplitude modulated signal. The second amplitude modulator amplitude modulates a second carrier signal with a second input signal and provides a second amplitude modulated signal. The summer sums the first and second amplitude modulated signals and provides a quadrature modulated signal that is both amplitude and phase modulated. The first and second input signals may be obtained based on absolute values of first and second modulating signals, respectively. The first and second carrier signals have phases determined based on the sign of the first and second modulating signals, respectively. Each amplitude modulator may be implemented with a class-E amplifier.

摘要翻译： 描述了可以使用幅度调制器执行正交调制的双极调制器。 在一种设计中，双极调制器包括第一和第二幅度调制器和夏季。 第一幅度调制器利用第一输入信号调制第一载波信号并提供第一幅度调制信号。 第二幅度调制器利用第二输入信号幅度调制第二载波信号，并提供第二幅度调制信号。 夏季对第一和第二幅度调制信号进行求和，并提供幅度和相位调制的正交调制信号。 可以分别基于第一和第二调制信号的绝对值来获得第一和第二输入信号。 第一和第二载波信号分别基于第一和第二调制信号的符号确定相位。 每个幅度调制器可以用E类放大器来实现。

公开(公告)号：US08060041B2

公开(公告)日：2011-11-15

申请号：US11352487

申请日：2006-02-09

申请人： Gary John Ballantyne

发明人： Gary John Ballantyne

IPC分类号： H04B17/02 ,  H04B1/16

CPC分类号： H04B1/109 ,  H04W52/0245 ,  Y02D70/1222 ,  Y02D70/1242 ,  Y02D70/144 ,  Y02D70/164 ,  Y02D70/40

摘要： In general, the disclosure is directed to techniques for combining a high performance receiver and a low power receiver within a wireless communication device (WCD) to reduce power consumption. Upon receiving a signal from a base station, a controller within the WCD detects one or more channel conditions of a radio frequency (RF) environment between the base station and the WCD. The controller selects a high performance receiver to process the received signal when the RF environment is unfavorable and selects a low power receiver to process the received signal when the RF environment is favorable. In this manner, the WCD implements an adaptive receiver that adapts its receiver structure according to RF channel conditions.

摘要翻译： 通常，本公开涉及用于组合无线通信设备（WCD）内的高性能接收机和低功率接收机以降低功耗的技术。 在从基站接收到信号时，WCD内的控制器检测基站和WCD之间的射频（RF）环境的一个或多个信道条件。 当RF环境不利时，控制器选择高性能接收机处理接收信号，并且当RF环境有利时选择低功率接收机来处理接收信号。 以这种方式，WCD实现了根据RF信道条件来适应其接收机结构的自适应接收机。

公开(公告)号：US20100323641A1

公开(公告)日：2010-12-23

申请号：US12489380

申请日：2009-06-22

申请人： Vladimir Aparin ,  Gary John Ballantyne

发明人： Vladimir Aparin ,  Gary John Ballantyne

IPC分类号： H04B1/04

CPC分类号： H03F1/34 ,  H03F1/3258

摘要： Techniques for mitigating nonlinearity of circuits with both pre-distortion and feedback are described. An apparatus may include at least one circuit (e.g., an upconverter, a power amplifier, etc.), a pre-distortion circuit, and a feedback circuit. The circuit(s) may generate an output signal having distortion components due to their nonlinearity. The pre-distortion circuit may receive an input signal and generate a pre-distorted signal based on at least one coefficient determined by the nonlinearity of the circuit(s). The pre-distortion circuit may adaptively determine the coefficient(s) based on the input signal and an error signal. The feedback circuit may generate the error signal based on the input signal and the output signal and may filter the error signal to obtain a filtered error signal. The circuit(s) may process the pre-distorted signal and the filtered error signal to generate the output signal, which may have attenuated distortion components due to pre-distortion and feedback.

摘要翻译： 描述了减轻预失真和反馈的电路非线性的技术。 装置可以包括至少一个电路（例如，上变频器，功率放大器等），预失真电路和反馈电路。 电路可以由于它们的非线性而产生具有失真分量的输出信号。 预失真电路可以接收输入信号，并且基于由电路的非线性确定的至少一个系数产生预失真信号。 预失真电路可以基于输入信号和误差信号自适应地确定系数。 反馈电路可以基于输入信号和输出信号产生误差信号，并且可以对误差信号进行滤波以获得滤波后的误差信号。 电路可以处理预失真信号和滤波后的误差信号以产生输出信号，其可能由于预失真和反馈而具有衰减的失真分量。

公开(公告)号：US07728690B2

公开(公告)日：2010-06-01

申请号：US11875766

申请日：2007-10-19

申请人： Gary John Ballantyne

发明人： Gary John Ballantyne

IPC分类号： H03C3/08 ,  H03C3/06 ,  H03L7/093

CPC分类号： H03C3/09 ,  H03C3/08

摘要： Techniques to compensate for nonlinearity of a tuning function of an oscillator are described. The tuning nonlinearity of the oscillator may be modeled as a disturbance input to the oscillator and may be compensated with an equal but opposite disturbance. In one design, a nonlinearity correction signal to compensate for the tuning nonlinearity may be generated, e.g., based on a phase error signal in a phase-locked loop (PLL) and a scaling factor determined adaptively. The nonlinearity correction signal may compensate for the n-th (e.g., second) order tuning nonlinearity, and an n-th order (e.g., squared) modulating signal may be used to derive the scaling factor and the nonlinearity correction signal. A control signal for the oscillator may be generated based on the nonlinearity correction signal and possibly one or more other signals. The control signal may be applied to the oscillator to adjust the oscillation frequency of the oscillator.

摘要翻译： 描述了补偿振荡器的调谐功能的非线性的技术。 振荡器的调谐非线性可以被建模为对振荡器的干扰输入，并且可以用相等但相反的干扰来补偿。 在一种设计中，可以例如基于锁相环（PLL）中的相位误差信号和自适应确定的缩放因子来产生补偿调谐非线性的非线性校正信号。 非线性校正信号可以补偿第n（例如，第二）阶调谐非线性，并且可以使用n阶（例如，平方）调制信号来导出缩放因子和非线性校正信号。 可以基于非线性校正信号和可能的一个或多个其他信号来产生用于振荡器的控制信号。 控制信号可以施加到振荡器以调节振荡器的振荡频率。

公开(公告)号：US20090268859A1

公开(公告)日：2009-10-29

申请号：US12111541

申请日：2008-04-29

申请人： Bo Sun ,  Gary John Ballantyne ,  Gurkanwal Singh Sahota

发明人： Bo Sun ,  Gary John Ballantyne ,  Gurkanwal Singh Sahota

IPC分类号： H03D3/24

CPC分类号： H03L7/00 ,  H03L7/0802 ,  H03L2207/50

摘要： An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.

摘要翻译： 一种包括可编程频率装置的装置，其适于产生从一组不同频率时钟中选择的参考时钟，其中所述可编程频率装置还适于在所述不同频率之间切换时维持所述参考时钟的触发边沿的相同的时间关系 时钟。 该装置还包括使用所选择的参考时钟来建立输入信号和输出信号之间的预定相位关系的锁相环（PLL），例如数字PLL（DPLL）。 通过在不同频率时钟之间切换时保持参考时钟的基本相同的时间关系，在改变参考时钟的同时，锁相环（PLL）的连续和有效操作不会受到明显干扰。 这可以用于控制设备的功耗。

公开(公告)号：US08269563B2

公开(公告)日：2012-09-18

申请号：US12136690

申请日：2008-06-10

申请人： Gary John Ballantyne

发明人： Gary John Ballantyne

IPC分类号： H03L7/085 ,  H03L7/089 ,  H03L7/099

CPC分类号： H03L7/099 ,  H03L2207/50 ,  H04B1/69

摘要： A digitally-controlled oscillator (DCO) of a PLL is dithered such that a DCO_OUT signal has a frequency that changes at dithered intervals. In one example, the DCO receives an undithered stream of incoming digital tuning words, and receives a dithered reference clock signal REFD, and outputs the DCO_OUT signal such that its frequency changes occur at dithered intervals. Where the PLL is employed in the local oscillator of a cellular telephone transmitter, the novel dithering of the DCO spreads digital image noise out in frequency such that less digital image noise is present at a particular frequency offset from the main local oscillator frequency. Spreading digital image noise out in frequency allows a noise specification to be met without having to increase the frequency of the PLL reference clock. By avoiding increasing the frequency of the reference clock to meet the noise specification, increases in power consumption are avoided.

摘要翻译： PLL的数字控制振荡器（DCO）抖动，使得DCO_OUT信号具有以抖动间隔变化的频率。 在一个示例中，DCO接收输入的数字调谐字的未传输流，并接收抖动参考时钟信号REFD，并输出DCO_OUT信号，使得其频率变化以抖动间隔发生。 在蜂窝电话发射机的本地振荡器中使用PLL的情况下，DCO的新颖抖动以频率扩展数字图像噪声，使得在与主本地振荡器频率偏移的特定频率处存在较少的数字图像噪声。 以频率扩展数字图像噪声允许满足噪声规范，而不必增加PLL参考时钟的频率。 通过避免增加参考时钟的频率以满足噪声规范，避免了功耗的增加。

公开(公告)号：US08054116B2

公开(公告)日：2011-11-08

申请号：US12018343

申请日：2008-01-23

申请人： Gary John Ballantyne

发明人： Gary John Ballantyne

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  G04F10/005 ,  H03L2207/50

摘要： Techniques for dithering quantization thresholds of time-to-digital converters (TDC's) in all-digital phase-locked loops (ADPLL's) are disclosed. In an embodiment, the delay introduced by an individual buffer in a TDC delay line may be dithered. In another embodiment, the delay associated with the TDC delay line may be extended by a fixed amount to accommodate dithering of the zero-delay threshold.

摘要翻译： 公开了用于在全数字锁相环（ADPLL）中抖动时 - 数转换器（TDC）的量化阈值的技术。 在一个实施例中，由TDC延迟线中的单个缓冲器引入的延迟可以是抖动的。 在另一个实施例中，与TDC延迟线相关联的延迟可以扩展固定的量以适应零延迟阈值的抖动。

公开(公告)号：US08045669B2

公开(公告)日：2011-10-25

申请号：US11947587

申请日：2007-11-29

申请人： Gary John Ballantyne ,  Bo Sun

发明人： Gary John Ballantyne ,  Bo Sun

IPC分类号： H03D3/04

CPC分类号： H03L7/10 ,  H03L7/085 ,  H03L7/087 ,  H03L2207/50

摘要： In one aspect, a digital PLL (DPLL) operates based on fractional portions of input and output phases. The DPLL accumulates at least one input signal to obtain an input phase. The DPLL determines a fractional portion of an output phase based on a phase difference between an oscillator signal from an oscillator and a reference signal, e.g., using a time-to-digital converter (TDC). The DPLL determines a phase error based on the fractional portion of the input phase and the fractional portion of the output phase. The DPLL then generates a control signal for the oscillator based on the phase error. In another aspect, a DPLL includes a synthesized accumulator that determines a coarse output phase by keeping track of the number of oscillator signal cycles based on the reference signal.

摘要翻译： 在一个方面，数字PLL（DPLL）基于输入和输出相位的小数部分进行操作。 DPLL累加至少一个输入信号以获得输入相位。 DPLL基于来自振荡器的振荡器信号与参考信号之间的相位差（例如使用时间 - 数字转换器（TDC））来确定输出相位的小数部分。 DPLL根据输入相位的小数部分和输出相位的小数部分确定相位误差。 DPLL然后基于相位误差产生振荡器的控制信号。 在另一方面，DPLL包括合成的累加器，其通过基于参考信号跟踪振荡器信号周期的数量来确定粗略的输出相位。