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9 条记录 (耗时 0.028 秒)

    Method and apparatus to control core logic temperature
    2.
    发明授权
    Method and apparatus to control core logic temperature 失效
    控制核心逻辑温度的方法和装置

    公开(公告)号：US06173217B2

    公开(公告)日：2001-01-09

    申请号：US08990711

    申请日：1997-12-15

    申请人： Zohar Bogin ,  Vincent E. VonBokern

    发明人： Zohar Bogin ,  Vincent E. VonBokern

    IPC分类号： G05D2300

    CPC分类号： G11C5/06 ,  G06F1/206 ,  G06F13/161 ,  G11C5/04 ,  G11C5/143 ,  G11C8/20

    摘要： A method for controlling core logic temperature. The core logic having a memory controller and memory components coupled to system memory. The method having the step of determining access rate to the system memory through the core logic and controlling the temperature of the core logic by adjusting the access rate.

    摘要翻译： 一种控制核心逻辑温度的方法。 核心逻辑具有存储器控制器和耦合到系统存储器的存储器组件。 该方法具有通过核心逻辑确定对系统存储器的访问速率并通过调整访问速率来控制核心逻辑的温度的步骤。

    Abort of DRAM read ahead when PCI read multiple has ended
    3.
    发明授权
    Abort of DRAM read ahead when PCI read multiple has ended 失效
    当PCI读取多个已经结束时，DRAM的中止被读取

    公开(公告)号：US06314472B1

    公开(公告)日：2001-11-06

    申请号：US09203127

    申请日：1998-12-01

    申请人： Tuong P. Trieu ,  David D. Lent ,  Ashish S. Gadagkar ,  Vincent E. VonBokern ,  Zohar Bogin

    发明人： Tuong P. Trieu ,  David D. Lent ,  Ashish S. Gadagkar ,  Vincent E. VonBokern ,  Zohar Bogin

    IPC分类号： G06F300

    CPC分类号： G06F13/161

    摘要： A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.

    摘要翻译： 提供计算机系统。 计算机系统包括主机处理器（HP），系统存储器（SM）以及输入/输出（I / O）主设备，以执行对SM的连续数据流的读取。 计算机系统还包括耦合到HP，SM和I / O主设备的桥。 当I / O主设备从SM读取连续的数据流时，桥接器向前读取SM。 响应于I / O主设备的脱离接口，桥接器在对SM进行访问提交之前中止对SM的预读访问。

    Accelerated graphics port expedite cycle throttling control mechanism
    5.
    发明授权
    Accelerated graphics port expedite cycle throttling control mechanism 失效
    加速图形端口加快循环调节控制机制

    公开(公告)号：US06784890B1

    公开(公告)日：2004-08-31

    申请号：US09033529

    申请日：1998-03-02

    申请人： Brian L. Bergeson ,  Zohar Bogin ,  Vincent E. VonBokern

    发明人： Brian L. Bergeson ,  Zohar Bogin ,  Vincent E. VonBokern

    IPC分类号： G06F1318

    CPC分类号： G06F13/1642

    摘要： A method for controlling expedite cycles having the steps of determining the number of clock cycles devoted to expedite data transfer requests made to a component during a predetermined monitoring window and guaranteeing a minimum number of clock cycles processing non-expedite requests during the monitoring window.

    摘要翻译： 一种用于控制加速循环的方法，其具有确定用于在预定监视窗口期间对组件进行的数据传送请求的时钟周期数量的步骤，并且确保在监视窗口期间处理非加速请求的最小数量的时钟周期。

    Apparatus and method for preventing access to SMRAM space through AGP addressing
    6.
    发明授权
    Apparatus and method for preventing access to SMRAM space through AGP addressing 失效
    通过AGP寻址防止访问SMRAM空间的装置和方法

    公开(公告)号：US06192455B1

    公开(公告)日：2001-02-20

    申请号：US09050627

    申请日：1998-03-30

    申请人： Zohar Bogin ,  Vincent E. VonBokern

    发明人： Zohar Bogin ,  Vincent E. VonBokern

    IPC分类号： G06F1200

    CPC分类号： G06F12/1036 ,  G06F12/1441

    摘要： A method for preventing access to a system management random access memory (SMRAM) space is disclosed. The method intercepts access to an accelerated graphics port (AGP) aperture memory space and re-directs the access to non-SMRAM space if the access is directed to the SMRAM space.

    摘要翻译： 公开了一种防止访问系统管理随机存取存储器（SMRAM）空间的方法。 该方法拦截对加速图形端口（AGP）光圈存储器空间的访问，并且如果访问指向SMRAM空间，则重新引导对非SMRAM空间的访问。

    AGP read and CPU wire coherency
    7.
    发明授权
    AGP read and CPU wire coherency 失效
    AGP读取和CPU线的一致性

    公开(公告)号：US6157397A

    公开(公告)日：2000-12-05

    申请号：US50381

    申请日：1998-03-30

    申请人： Zohar Bogin ,  Narendra S. Khandekar ,  Vincent E. VonBokern

    发明人： Zohar Bogin ,  Narendra S. Khandekar ,  Vincent E. VonBokern

    IPC分类号： G06F3/14 ,  G06F13/00

    CPC分类号： G06F3/14

    摘要： A method for graphics device read and processor write coherency receives a write request from a processor to write data to a storage element for a component to read and flushes the data to the storage element prior to the component reading the address associated with the data in the storage element.

    摘要翻译： 用于图形设备读取和处理器写入一致性的方法从处理器接收写入请求，以将数据写入存储元件，以便组件在组件读取与数据相关联的地址之前将数据读取和刷新到存储元件 存储元件

    Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio
    8.
    发明授权
    Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio 失效
    在以非整数频率比工作的同步时钟域之间传播信号的方法和装置

    公开(公告)号：US5961649A

    公开(公告)日：1999-10-05

    申请号：US985391

    申请日：1997-12-04

    申请人： Narendra Khandekar ,  Ashish S. Gadagkar ,  Robert F. Kubick ,  Vincent E. VonBokern ,  Manish Muthal

    发明人： Narendra Khandekar ,  Ashish S. Gadagkar ,  Robert F. Kubick ,  Vincent E. VonBokern ,  Manish Muthal

    IPC分类号： G06F5/06 ,  G06F1/72

    CPC分类号： G06F5/06

    摘要： A method of transmitting a signal from a relatively fast clock domain to a relatively slow clock domain is described. The fast and slow clock domains operate according to respective fast and slow clock signals that are substantially synchronized and that have respective frequencies that are non-integer multiples. A first state of an input signal is latched at the commencement of a first period of the fast clock signal, the commencement of the first period of the fast clock signal being substantially coincident with the commencement of a first period of the slow clock signal. In response to the latching of the first state of the input signal, a first output signal is generated and held over the first period, and at least one further period, of the fast clock signal. The first output signal is then latched in the second time domain in response to the commencement of a second period of the slow clock signal, the second period being immediately subsequent to the first period of the slow clock signal.

    摘要翻译： 描述了将信号从相对较快的时钟域发送到相对慢的时钟域的方法。 快速和慢速时钟域根据基本同步的相应的快速和慢速时钟信号进行操作，并且具有非整数倍的相应频率。 输入信号的第一状态在快时钟信号的第一周期的开始时被锁存，快速时钟信号的第一周期的开始基本上与慢时钟信号的第一周期的开始一致。 响应于输入信号的第一状态的锁存，在快速时钟信号的第一周期和至少另外一个周期内产生并保持第一输出信号。 响应于慢时钟信号的第二周期的开始，第一输出信号在第二时域被锁存，第二周期紧接在慢时钟信号的第一周期之后。

    Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio
    9.
    发明授权
    Method and apparatus for propagating a signal between synchronous clock domains operating at a non-integer frequency ratio 失效
    在以非整数频率比工作的同步时钟域之间传播信号的方法和装置

    公开(公告)号：US6049887A

    公开(公告)日：2000-04-11

    申请号：US985390

    申请日：1997-12-04

    申请人： Narendra Khandekar ,  Ashish S. Gadagkar ,  Robert F. Kubick ,  Vincent E. VonBokern ,  Manish Muthal

    发明人： Narendra Khandekar ,  Ashish S. Gadagkar ,  Robert F. Kubick ,  Vincent E. VonBokern ,  Manish Muthal

    IPC分类号： G06F1/10 ,  G06F11/00

    CPC分类号： G06F1/10

    摘要： A method of transmitting a signal from a first clock domain to a second clock domain commences with the generation of first and second clock signals. The first and second clock signals are substantially synchronous and have respective frequencies that are non-integer multiples. A first signal, which is generated in the first clock domain responsive to a transition of the first clock signal that is substantially coincident with a transition of the second clock signal, is prevented from being latched in the second clock domain responsive to the transition of the second clock signal. The first clock signal is prevented from being latched for a time period which is greater than a maximum clock skew which may exist between the first and second clock signals.

    摘要翻译： 将信号从第一时钟域发送到第二时钟域的方法从产生第一和第二时钟信号开始。 第一和第二时钟信号基本上是同步的并且具有非整数倍的相应频率。 响应于基本上与第二时钟信号的转换相关的第一时钟信号的转变而在第一时钟域中产生的第一信号被防止被锁存在第二时钟域中， 第二个时钟信号。 防止第一时钟信号被锁存大于可能存在于第一和第二时钟信号之间的最大时钟偏移的时间段。