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16 条记录 (耗时 0.033 秒)

    Method and apparatus for power management in a memory subsystem
    2.
    发明授权
    Method and apparatus for power management in a memory subsystem 有权
    存储器子系统中的电源管理方法和装置

    公开(公告)号：US06442698B2

    公开(公告)日：2002-08-27

    申请号：US09187565

    申请日：1998-11-04

    申请人： Puthiya K. Nizar

    发明人： Puthiya K. Nizar

    IPC分类号： G06F100

    CPC分类号： G06F1/3225 ,  G06F1/3275 ,  G06F12/06 ,  Y02D10/13 ,  Y02D10/14

    摘要： According to one embodiment, the present invention discloses a method of managing power in a memory system. The memory system includes a plurality of memory devices. Each one of the memory devices is grouped in a first group or a second group. First, access to a memory device is requested. It is next determined whether the requested memory device is located in the first group. If the requested memory device is not located within the first group, it is determined whether the first group is filled to capacity. If the first group is not filled to capacity, the requested memory device is transferred to the first group. According to a further embodiment, each one of the memory devices grouped into the first group is further grouped in to a first subgroup or a second subgroup.

    摘要翻译： 根据一个实施例，本发明公开了一种管理存储器系统中的电力的方法。 存储器系统包括多个存储器件。 每个存储器件被分组在第一组或第二组中。 首先，请求访问存储设备。 接下来确定所请求的存储器件是否位于第一组中。 如果请求的存储设备不位于第一组内，则确定第一组是否被填充到容量。 如果第一组未被装入容量，则所请求的存储器件被传送到第一组。 根据另一实施例，分组到第一组中的每个存储器件进一步分组到第一子组或第二子组。

    Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices
    3.
    发明授权
    Method and apparatus for memory address decode in memory subsystems supporting a large number of memory devices 有权
    用于支持大量存储器件的存储器子系统中的存储器地址解码的方法和装置

    公开(公告)号：US06252821B1

    公开(公告)日：2001-06-26

    申请号：US09474570

    申请日：1999-12-29

    申请人： Puthiya K. Nizar ,  Michael W. Williams

    发明人： Puthiya K. Nizar ,  Michael W. Williams

    IPC分类号： G11C800

    CPC分类号： G11C8/10

    摘要： One embodiment of the invention is a method for decoding a memory access address. A portion of the memory access address is compared to a plurality of boundary values, each of the plurality of boundary values representing an uppermost address for a group of memory devices, each of the memory devices in the group having the same configuration. A group number is generated that represents an addressed group that contains an addressed memory device that contains the memory access address. A device number is generated that represents the location of the addressed memory device within the addressed group. A device selection signal is generated responsive to the group number and the device number.

    摘要翻译： 本发明的一个实施例是用于对存储器访问地址进行解码的方法。 将存储器访问地址的一部分与多个边界值进行比较，多个边界值中的每一个表示一组存储器设备的最高地址，组中的每个存储器件具有相同的配置。 生成组号，其表示包含存储器访问地址的寻址存储器设备的寻址组。 生成一个设备编号，表示寻址的组中寻址的存储器件的位置。 根据组号和设备编号产生设备选择信号。

    Memory transceiver to couple an additional memory channel to an existing memory channel
    4.
    发明授权
    Memory transceiver to couple an additional memory channel to an existing memory channel 失效
    存储收发器将附加存储器通道耦合到现有存储器通道

    公开(公告)号：US06467013B1

    公开(公告)日：2002-10-15

    申请号：US09409953

    申请日：1999-09-30

    申请人： Puthiya K. Nizar

    发明人： Puthiya K. Nizar

    IPC分类号： G06F1200

    CPC分类号： G06F13/4045 ,  G06F13/1684

    摘要： A memory repeater hub comprising a main memory channel interface circuit, an expansion control channel interface circuit, and an expansion memory channel interface circuit. The main memory channel interface circuit receives a memory control packet and a memory data packet from a main memory channel. The expansion control channel interface circuit receives a first expansion control packet and a second expansion control packet from an expansion control channel. The expansion memory channel interface circuit selectively transmits the memory control packet to an expansion memory channel responsive to the first expansion control packet, and selectively transmits the memory data packet to the expansion memory channel responsive to the second expansion control packet.

    摘要翻译： 一种存储中继器集线器，包括主存储器通道接口电路，扩展控制通道接口电路和扩展存储器通道接口电路。 主存储器通道接口电路从主存储器通道接收存储器控制分组和存储器数据分组。 扩展控制信道接口电路从扩展控制信道接收第一扩展控制分组和第二扩展控制分组。 扩展存储器通道接口电路响应于第一扩展控制分组选择性地将存储器控制分组发送到扩展存储器通道，并且响应于第二扩展控制分组选择性地将存储器数据分组发送到扩展存储器通道。

    Method and apparatus for configuring and initializing a memory device and a memory channel
    6.
    发明授权
    Method and apparatus for configuring and initializing a memory device and a memory channel 失效
    用于配置和初始化存储器件和存储器通道的方法和装置

    公开(公告)号：US06636957B2

    公开(公告)日：2003-10-21

    申请号：US09779072

    申请日：2001-02-07

    申请人： William A. Stevens ,  Puthiya K. Nizar

    发明人： William A. Stevens ,  Puthiya K. Nizar

    IPC分类号： G06F1200

    CPC分类号： G06F13/4243

    摘要： A method and apparatus for configuring and/or initializing memory devices. A disclosed method initializes a memory controller and a plurality of memory controller configuration registers. Serial identification numbers are assigned to memory devices coupled to the memory controller. Additionally, groups of device identification numbers, which are based at least in part on the memory device sizes, are assigned to the memory devices, and the memory devices are enabled.

    摘要翻译： 一种用于配置和/或初始化存储器件的方法和装置。 所公开的方法初始化存储器控制器和多个存储器控制器配置寄存器。 串行识别号被分配给耦合到存储器控制器的存储器件。 此外，至少部分地基于存储器设备大小的设备标识号码组被分配给存储器设备，并且存储器设备被使能。

    Method and apparatus for supporting SDRAM memory
    8.
    发明授权
    Method and apparatus for supporting SDRAM memory 失效
    用于支持SDRAM存储器的方法和装置

    公开(公告)号：US06889284B1

    公开(公告)日：2005-05-03

    申请号：US09420887

    申请日：1999-10-19

    申请人： Puthiya K. Nizar ,  Khong S. Foo

    发明人： Puthiya K. Nizar ,  Khong S. Foo

    IPC分类号： G06F13/36 ,  G06F13/40 ,  G06F13/42

    CPC分类号： G06F13/4243 ,  G06F13/4004

    摘要： A memory translation hub comprising a memory channel interface, a memory bus interface, and a command generator coupled to the memory channel interface and to the memory bus interface. The memory channel interface receives a memory control packet from a memory channel. The memory bus interface provides a memory bus. The command generator causes the memory bus interface to provide memory control signals on the memory bus responsive to the memory control packet.

    摘要翻译： 包括存储器通道接口，存储器总线接口和耦合到存储器通道接口和存储器总线接口的命令发生器的存储器转换集线器。 存储器通道接口从存储器通道接收存储器控制分组。 内存总线接口提供内存总线。 命令发生器使得存储器总线接口响应于存储器控制分组在存储器总线上提供存储器控制信号。

    Means to extend tTR range of RDRAMS via the RDRAM memory controller
    10.
    发明授权
    Means to extend tTR range of RDRAMS via the RDRAM memory controller 有权
    意味着通过RDRAM存储器控制器扩展RDRAMS的tTR范围

    公开(公告)号：US06516396B1

    公开(公告)日：2003-02-04

    申请号：US09470300

    申请日：1999-12-22

    申请人： Andrew M. Volk ,  Puthiya K. Nizar

    发明人： Andrew M. Volk ,  Puthiya K. Nizar

    IPC分类号： G06F1200

    CPC分类号： G06F13/1689

    摘要： A method and system for extending tTR range of memory devices coupled to a memory devices is described. A first group of memory devices and a second group of memory devices are identified. The first group includes memory devices located close to a memory controller and the second group includes memory devices located a distance away from the memory controller. Commands to access memory devices in the first and second groups are sent. A command to the first group is sent with a transitional delay when the command to the first group follows a command to the second group. In response to the commands, data from the first and second groups is received.

    摘要翻译： 描述了用于扩展耦合到存储器件的存储器件的tTR范围的方法和系统。 识别第一组存储器件和第二组存储器件。 第一组包括位于存储器控制器附近的存储器件，第二组包括距离存储器控制器一定距离的存储器件。 发送访问第一组和第二组中的存储设备的命令。 当对第一组的命令遵循对第二组的命令时，向第一组发送的命令具有过渡延迟。 响应于这些命令，接收来自第一组和第二组的数据。