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    System and method for suppression of peaking in an external LC filter of a buck regulator
    5.
    发明授权
    System and method for suppression of peaking in an external LC filter of a buck regulator 有权
    抑制降压调节器外部LC滤波器峰值的系统和方法

    公开(公告)号：US09071136B2

    公开(公告)日：2015-06-30

    申请号：US13645280

    申请日：2012-10-04

    Applicant: QUALCOMM Incorporated

    Inventor： Ankit Srivastava ,  Vijayakumar Dhanasekaran

    IPC: G05F1/563 ,  H02M3/156 ,  H02M1/00 ,  H02M1/12

    CPC classification number: H02M3/156 ,  H02M1/12 ,  H02M2001/0025 ,  H02M2001/0032 ,  Y02B70/16

    Abstract: Disclosed are systems and methods for suppressing voltage peaking in a buck regulator. In one aspect, a buck regulator comprises: a pulse-width modulator (PWM) that generates a pulsed signal; a switch operable to selectively connect the regulator to a DC power supply in response to the pulsed signal and output a pulsed output DC signal; a filter for filtering out high frequency noise from the pulsed output DC signal and generating a regulated output signal; an integrator for comparing the pulsed output DC signal with a reference voltage signal and generating an error signal for input to the PWM; a subtractor operable to subtract the reference voltage signal from the filtered output signal to generate an error feedback signal; and an adder operable to add the error feedback signal to the error signal for input to the pulse-width modulator in order to suppress voltage peaks in the filtered output signal.

    Abstract translation: 公开了用于抑制降压调节器中的峰值电压的系统和方法。 一方面，降压调节器包括：产生脉冲信号的脉冲宽度调制器（PWM）; 开关，其可操作以响应于所述脉冲信号选择性地将调节器连接到DC电源并输出脉冲输出DC信号; 用于从脉冲输出DC信号滤除高频噪声并产生调节输出信号的滤波器; 用于将脉冲输出DC信号与参考电压信号进行比较并产生用于输入到PWM的误差信号的积分器; 减法器，用于从滤波的输出信号中减去参考电压信号以产生误差反馈信号; 以及加法器，用于将误差反馈信号添加到误差信号以输入到脉宽调制器，以便抑制经滤波的输出信号中的电压峰值。

    SYSTEM AND METHOD FOR SUPPRESSION OF PEAKING IN AN EXTERNAL LC FILTER OF A BUCK REGULATOR
    6.
    发明申请
    SYSTEM AND METHOD FOR SUPPRESSION OF PEAKING IN AN EXTERNAL LC FILTER OF A BUCK REGULATOR 有权
    用于抑制BUCK调节器的外部LC滤波器中的峰值的系统和方法

    公开(公告)号：US20130257398A1

    公开(公告)日：2013-10-03

    申请号：US13645280

    申请日：2012-10-04

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ankit Srivastava ,  Vijayakumar Dhanasekaran

    IPC: G05F1/62

    CPC classification number: H02M3/156 ,  H02M1/12 ,  H02M2001/0025 ,  H02M2001/0032 ,  Y02B70/16

    Abstract: Disclosed are systems and methods for suppressing voltage peaking in a buck regulator. In one aspect, a buck regulator comprises: a pulse-width modulator (PWM) that generates a pulsed signal; a switch operable to selectively connect the regulator to a DC power supply in response to the pulsed signal and output a pulsed output DC signal; a filter for filtering out high frequency noise from the pulsed output DC signal and generating a regulated output signal; an integrator for comparing the pulsed output DC signal with a reference voltage signal and generating an error signal for input to the PWM; a subtractor operable to subtract the reference voltage signal from the filtered output signal to generate an error feedback signal; and an adder operable to add the error feedback signal to the error signal for input to the pulse-width modulator in order to suppress voltage peaks in the filtered output signal.

    Abstract translation: 公开了用于抑制降压调节器中的峰值电压的系统和方法。 一方面，降压调节器包括：产生脉冲信号的脉冲宽度调制器（PWM）; 开关，其可操作以响应于脉冲信号选择性地将调节器连接到DC电源并输出脉冲输出DC信号; 用于从脉冲输出DC信号滤除高频噪声并产生调节输出信号的滤波器; 用于将脉冲输出DC信号与参考电压信号进行比较并产生用于输入到PWM的误差信号的积分器; 减法器，用于从滤波的输出信号中减去参考电压信号以产生误差反馈信号; 以及加法器，用于将误差反馈信号添加到误差信号以输入到脉宽调制器，以便抑制经滤波的输出信号中的电压峰值。

    Successive approximation register (SAR) analog-to-digital converter (ADC) with passive gain scaling
    9.
    发明授权
    Successive approximation register (SAR) analog-to-digital converter (ADC) with passive gain scaling 有权

    公开(公告)号：US10277244B1

    公开(公告)日：2019-04-30

    申请号：US16046053

    申请日：2018-07-26

    Applicant: QUALCOMM Incorporated

    Inventor： Ankit Srivastava ,  Sameer Wadhwa ,  Shunxi Wang

    IPC: H03M1/38 ,  H03M1/46 ,  H03G3/30

    Abstract: Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a passive gain scaling architecture. Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a plurality of capacitive elements, a plurality of switches coupled to the plurality of capacitive elements, and SAR logic having an output coupled to control inputs of the plurality of switches. The circuit also includes a comparator having an output coupled to an input of the SAR logic, a sampling circuit coupled to an input node of the circuit, and a first capacitive element coupled in series between the sampling circuit and the plurality of capacitive elements.

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