公开(公告)号：US20140310468A1

公开(公告)日：2014-10-16

申请号：US13933337

申请日：2013-07-02

Applicant: QUALCOMM Incorporated

Inventor： Thomas Philip Speier ,  Eric F. Robinson ,  Jaya Prakash Subramaniam Ganasan ,  Thomas Andrew Sartorius ,  James Norris Dieffenderfer

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0831 ,  G06F15/173

Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.

Abstract translation: 针对具有两个或多个处理器的多处理器描述技术，这增加了独占命令以独占状态取高速缓存行的机会，这导致执行存储排他时的性能提高。 读取优先排序的新总线操作被用作对请求主机可能存储到高速缓存行的其他高速缓存的提示，并且如果可能的话，其他高速缓存应该给排队。 在大多数情况下，这将导致其他主人员排队，并且请求主人将线独占。 在大多数情况下，两个或多个处理器不会同时对同一地址执行信号量管理序列。 因此，请求主机的负载排他能够在独占状态下取高速缓存行增加次数。

公开(公告)号：US10386904B2

公开(公告)日：2019-08-20

申请号：US15086054

申请日：2016-03-31

Applicant: QUALCOMM Incorporated

Inventor： Jason Edward Podaima ,  Christophe Denis Bernard Avoinne ,  Manokanthan Somasundaram ,  Sina Dena ,  Paul Christopher John Wiercienski ,  Bohuslav Rychlik ,  Steven John Halter ,  Jaya Prakash Subramaniam Ganasan ,  Myil Ramkumar ,  Dipti Ranjan Pal

IPC: G06F1/26 ,  G06F1/10 ,  G06F1/324 ,  G06F1/3234 ,  G06F1/3287 ,  G06F12/08

Abstract: Methods and systems are disclosed for full-hardware management of power and clock domains related to a distributed virtual memory (DVM) network. An aspect includes transmitting, from a DVM initiator to a DVM network, a DVM operation, broadcasting, by the DVM network to a plurality of DVM targets, the DVM operation, and, based on the DVM operation being broadcasted to the plurality of DVM targets by the DVM network, performing one or more hardware optimizations comprising: turning on a clock domain coupled to the DVM network or a DVM target of the plurality of DVM targets that is a target of the DVM operation, increasing a frequency of the clock domain, turning on a power domain coupled to the DVM target based on the power domain being turned off, or terminating the DVM operation to the DVM target based on the DVM target being turned off.

公开(公告)号：US09594713B2

公开(公告)日：2017-03-14

申请号：US14484624

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Randall John Pascarella ,  Jaya Prakash Subramaniam Ganasan ,  Thuong Quang Truong ,  Gurushankar Rajamani ,  Joseph Gerald McDonald ,  Thomas Philip Speier

IPC: G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/4013 ,  G06F13/1621 ,  G06F13/4027 ,  G06F13/4059 ,  G06F13/4221

Abstract: Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.

Abstract translation: 公布了对弱排序域中的设备进行强有序的写入事务，并且公开了相关设备，方法和计算机可读介质。 在一个方面，主桥设备被配置为从一个或多个强排序的生成器设备接收强有序的写事务。 主桥设备向弱排序域中的一个或多个消费者设备发出强有序的写事务。 主桥设备检测不被一个或多个消费者设备的第一消费者设备接受的第一写事务。 对于在第一写入事务之后发出并由相应的消费者设备接受的一个或多个写入事务中的每一个，主桥设备向相应的消费者设备发送取消消息。 主桥设备重播第一个写入事务以及在第一次写入事务之后发出的一个或多个写入事务。

公开(公告)号：US09152595B2

公开(公告)日：2015-10-06

申请号：US13654653

申请日：2012-10-18

Applicant: QUALCOMM Incorporated

Inventor： Jaya Prakash Subramaniam Ganasan ,  Mark Michael Schaffer ,  Prudhvi N. Nooney ,  Perry Willmann Remaklus, Jr.

IPC: G06F1/32 ,  G06F13/40 ,  G06F15/173 ,  G06F13/368

CPC classification number: G06F13/4027 ,  G06F1/3287 ,  G06F13/368 ,  G06F13/4004 ,  G06F15/17375 ,  Y02D10/14 ,  Y02D10/151

Abstract: Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.

Abstract translation: 公开了基于处理器的系统混合环形总线互连以及相关设备，系统和方法。 在一个实施例中，提供了基于处理器的系统混合环形总线互连。 基于处理器的系统混合环形总线互连包括多个环形总线，每个环形总线具有总线宽度并且被配置为从请求者设备接收总线事务消息。 基于处理器的系统混合环形总线互连还包括耦合到环形总线的环形间路由器。 环形路由器被配置为基于请求者设备的带宽需求来动态地指导环形总线中的总线事务消息。 因此，由于更简单的开关配置，功率消耗比交叉开关互连更少。 此外，环形路由器允许提供可以基于带宽需求被动态地激活和去激活的多个环形总线。 当不需要基于处理器的系统混合环形总线互连的全带宽要求时，这提供了功率的保护。

公开(公告)号：US09921962B2

公开(公告)日：2018-03-20

申请号：US14863535

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Kun Xu ,  Thuong Quang Truong ,  Jaya Prakash Subramaniam Ganasan ,  Hien Minh Le ,  Cesar Aaron Ramirez

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/0815 ,  G06F12/0831

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/621 ,  Y02D10/13

Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.

公开(公告)号：US20170091095A1

公开(公告)日：2017-03-30

申请号：US14863535

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Kun Xu ,  Thuong Quang Truong ,  Jaya Prakash Subramaniam Ganasan ,  Hien Minh Le ,  Cesar Aaron Ramirez

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0831 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/621 ,  Y02D10/13

Abstract: Maintaining cache coherency using conditional intervention among multiple master devices is disclosed. In one aspect, a conditional intervention circuit is configured to receive intervention responses from multiple snooping master devices. To select a snooping master device to provide intervention data, the conditional intervention circuit determines how many snooping master devices have a cache line granule size the same as or larger than a requesting master device. If one snooping master device has a same or larger cache line granule size, that snooping master device is selected. If more than one snooping master device has a same or larger cache line granule size, a snooping master device is selected based on an alternate criteria. The intervention responses provided by the unselected snooping master devices are canceled by the conditional intervention circuit, and intervention data from the selected snooping master device is provided to the requesting master device.

公开(公告)号：US20130191572A1

公开(公告)日：2013-07-25

申请号：US13669629

申请日：2012-11-06

Applicant: QUALCOMM Incorporated

Inventor： Prudhvi N. Nooney ,  Jaya Prakash Subramaniam Ganasan ,  Barry Joe Wolford

IPC: G06F13/20

CPC classification number: G06F13/4036

Abstract: Methods and apparatus for transaction ordering to avoid bus deadlocks are provided. In an exemplary method, custom routing rules for data transport are defined for data transport between a plurality of masters and a plurality of slaves via a plurality of interconnects, based on a network topology and traffic profile. In an example, the customized rule allows a request address to arbitrate in a first phase of arbitration at a first interconnect in the plurality of interconnects prior to receiving write data associated with the request address at a second interconnect in the plurality of interconnects, and does not allow the request address to arbitrate during a subsequent second phase of arbitration unless the request address beats other competing address requests.

Abstract translation: 提供了交易排序以避免总线死锁的方法和装置。 在示例性方法中，基于网络拓扑和业务简档，定义用于数据传输的定制路由规则用于经由多个互连的多个主站和多个从站之间的数据传输。 在一个示例中，定制规则允许请求地址在多个互连中的第一互连处的仲裁的第一阶段中仲裁，然后在多个互连中的第二互连处接收与请求地址相关联的写入数据，并且 不允许请求地址在仲裁的后续第二阶段进行仲裁，除非请求地址与其他竞争地址请求相同。

公开(公告)号：US09990291B2

公开(公告)日：2018-06-05

申请号：US14863645

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Hien Minh Le ,  Thuong Quang Truong ,  Kun Xu ,  Jaya Prakash Subramaniam Ganasan ,  Cesar Aaron Ramirez

IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/16 ,  G06F13/40 ,  G06F13/42 ,  G06F12/0815 ,  G06F9/52

CPC classification number: G06F12/0831 ,  G06F9/524 ,  G06F12/0815 ,  G06F12/0833 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/42 ,  G06F2212/1008 ,  G06F2212/621

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

公开(公告)号：US20170091098A1

公开(公告)日：2017-03-30

申请号：US14863645

申请日：2015-09-24

Applicant: QUALCOMM Incorporated

Inventor： Hien Minh Le ,  Thuong Quang Truong ,  Kun Xu ,  Jaya Prakash Subramaniam Ganasan ,  Cesar Aaron Ramirez

IPC: G06F12/08 ,  G06F13/40 ,  G06F13/42 ,  G06F13/16

CPC classification number: G06F12/0831 ,  G06F9/524 ,  G06F12/0815 ,  G06F12/0833 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/42 ,  G06F2212/1008 ,  G06F2212/621

Abstract: Aspects disclosed herein include avoiding deadlocks in processor-based systems employing retry and in-order-response non-retry bus coherency protocols. In this regard, an interface bridge circuit is communicatively coupled to a first core device that implements a retry bus coherency protocol, and a second core device that implements an in-order-response non-retry bus coherency protocol. The interface bridge circuit receives a snoop command from the first core device, and forwards the snoop command to the second core device. While the snoop command is pending, the interface bridge circuit detects a potential deadlock condition between the first core device and the second core device. In response to detecting the potential deadlock condition, the interface bridge circuit is configured to send a retry response to the first core device. This enables the first core device to continue processing, thereby eliminating the potential deadlock condition.

公开(公告)号：US09292442B2

公开(公告)日：2016-03-22

申请号：US13933337

申请日：2013-07-02

Applicant: QUALCOMM Incorporated

Inventor： Thomas Philip Speier ,  Eric F. Robinson ,  Jaya Prakash Subramaniam Ganasan ,  Thomas Andrew Sartorius ,  James Norris Dieffenderfer

IPC: G06F12/08

CPC classification number: G06F12/0808 ,  G06F12/0811 ,  G06F12/0831 ,  G06F15/173

Abstract: Techniques are described for a multi-processor having two or more processors that increases the opportunity for a load-exclusive command to take a cache line in an Exclusive state, which results in increased performance when a store-exclusive is executed. A new bus operation read prefer exclusive is used as a hint to other caches that a requesting master is likely to store to the cache line, and, if possible, the other cache should give the line up. In most cases, this will result in the other master giving the line up and the requesting master taking the line Exclusive. In most cases, two or more processors are not performing a semaphore management sequence to the same address at the same time. Thus, a requesting master's load-exclusive is able to take a cache line in the Exclusive state an increased number of times.

Abstract translation: 针对具有两个或多个处理器的多处理器描述技术，这增加了独占命令以独占状态取高速缓存行的机会，这导致执行存储排他时的性能提高。 读取优先排序的新总线操作被用作对请求主机可能存储到高速缓存行的其他高速缓存的提示，并且如果可能的话，其他高速缓存应该给排队。 在大多数情况下，这将导致其他主人员排队，并且请求主人将线独占。 在大多数情况下，两个或多个处理器不会同时对同一地址执行信号量管理序列。 因此，请求主机的负载排他能够在独占状态下取高速缓存行增加次数。