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    Integrated circuit adaptive voltage scaling with de-aging
    4.
    发明授权
    Integrated circuit adaptive voltage scaling with de-aging 有权
    集成电路自适应电压缩放与衰老

    公开(公告)号：US09484892B1

    公开(公告)日：2016-11-01

    申请号：US14850801

    申请日：2015-09-10

    Applicant: QUALCOMM Incorporated

    Inventor： Mohammad Reza Kakoee ,  Shih-Hsin Jason Hu ,  Min Chen ,  Jasmin Smaila Ibrahimovic ,  Carlos Auyon ,  Sorin Adrian Dobre ,  Navid Toosizadeh ,  Nan Chen ,  Mohamed Waleed Allam

    IPC: G01R31/317 ,  H03K3/011 ,  H03K3/012

    CPC classification number: H03K3/011 ,  G01R31/2884 ,  G01R31/31727 ,  H03K3/012

    Abstract: An integrated circuit compensates for circuit aging by measuring the aging with an aging sensor and controlling a supply voltage based on the measured aging. The operating environment for the aging sensor can be set to reduce impacts of non-aging effects on the measured aging. For example, the operating environment can use a temperature inversion voltage. An initial aging measurement value which is the difference between an initial aged measurement and an initial unaged measurement can be stored on the integrated circuit. A core power reduction controller can use the measured aging and the stored initial aging measurement value to update a performance-sensor target value and then perform adaptive voltage scaling using the using the updated performance-sensor target value.

    Abstract translation: 集成电路通过使用老化传感器测量老化并根据测量的老化来控制电源电压来补偿电路老化。 老化传感器的操作环境可以设置为减少非老化对测量老化的影响。 例如，操作环境可以使用温度反转电压。 初始老化测量值与初始未老化测量值之差可以存储在集成电路上。 核心功率降低控制器可以使用测量的老化和存储的初始老化测量值来更新性能传感器目标值，然后使用更新的性能传感器目标值来执行自适应电压缩放。

    CIRCUITS AND METHODS PROVIDING VOLTAGE ADJUSTMENT AS PROCESSOR CORES BECOME ACTIVE
    6.
    发明申请
    CIRCUITS AND METHODS PROVIDING VOLTAGE ADJUSTMENT AS PROCESSOR CORES BECOME ACTIVE 有权
    提供电压调整的电路和方法，因为处理器的电压已经成为主动

    公开(公告)号：US20170068309A1

    公开(公告)日：2017-03-09

    申请号：US14849343

    申请日：2015-09-09

    Applicant: QUALCOMM Incorporated

    Inventor： Navid Toosizadeh ,  Mohammad Reza Kakoee ,  Shih-Hsin Jason Hu ,  Mohamed Waleed Allam

    IPC: G06F1/32

    CPC classification number: G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

    Abstract: A method including receiving an indication of a number of active processing units in a computer processor; in response to receiving the indication, determining an appropriate operating voltage margin for the computer processor; reducing an operating frequency of the active processing units in response to receiving the indication; adjusting a power supply to increase or decrease a voltage to the computer processor in accordance with the appropriate operating voltage margin; and increasing the operating frequency of the active processing units in response to an acknowledgment that the power supply has been adjusted.

    Abstract translation: 一种方法，包括在计算机处理器中接收多个活动处理单元的指示; 响应于接收到所述指示，确定所述计算机处理器的适当的工作电压裕度; 响应于接收到所述指示而减少所述活动处理单元的操作频率; 调整电源以根据适当的工作电压余量增加或减少计算机处理器的电压; 以及响应于已经调整了电源的确认来增加主动处理单元的操作频率。

    STATE-DEPENDENT CAPACITANCE ESTIMATION
    7.
    发明申请
    STATE-DEPENDENT CAPACITANCE ESTIMATION 有权
    状态依赖电容估计

    公开(公告)号：US20150198657A1

    公开(公告)日：2015-07-16

    申请号：US14157498

    申请日：2014-01-16

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ryan Michael Coutts ,  Mohamed Waleed Allam

    IPC: G01R31/28 ,  G01R27/26

    CPC classification number: G01R31/2851 ,  G01R27/2605 ,  G06F1/263 ,  G06F1/3287 ,  H03K19/0013 ,  H03K19/00315

    Abstract: Techniques for estimating state-dependent capacitance of a circuit are described herein. In one embodiment, a method for determining a circuit state for a circuit comprises determining a capacitance of the circuit for each one of a plurality of circuit states, and selecting one of the circuit states based on the determined capacitances.

    Abstract translation: 本文描述了用于估计电路的状态相关电容的技术。 在一个实施例中，一种用于确定电路的电路状态的方法包括确定多个电路状态中的每一个的电路的电容，以及基于确定的电容来选择电路状态之一。

    POWER DISTRIBUTION NETWORK (PDN) DROOP/OVERSHOOT MITIGATION
    8.
    发明申请
    POWER DISTRIBUTION NETWORK (PDN) DROOP/OVERSHOOT MITIGATION 有权
    电力分配网络（PDN）DROOP / OVERSHOOT MITIGATION

    公开(公告)号：US20170038789A1

    公开(公告)日：2017-02-09

    申请号：US14817057

    申请日：2015-08-03

    Applicant: QUALCOMM Incorporated

    Inventor： Dipti Ranjan Pal ,  Mohamed Waleed Allam ,  Ingyeom Kim ,  Paul Ivan Penzes

    IPC: G06F1/08 ,  G06F1/12

    CPC classification number: G06F1/08 ,  G06F1/12

    Abstract: Systems and methods for power distribution network (PDN) droop/overshoot mitigation are provided. In certain embodiments, overshoot is mitigated by ramping down a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an active mode to an idle mode. In certain embodiments, droop is mitigated by ramping up a frequency of a clock signal to a processor when the processor is switching clock frequencies and/or the processor is transitioning from an idle mode to an active mode.

    Abstract translation: 提供了配电网络（PDN）下垂/过冲缓解的系统和方法。 在某些实施例中，当处理器切换时钟频率和/或处理器从活动模式转换到空闲模式时，通过将时钟信号的频率降低到处理器来减轻过冲。 在某些实施例中，当处理器切换时钟频率和/或处理器从空闲模式转换到活动模式时，通过将时钟信号的频率上升到处理器来减轻下降。

    THERMAL SIMULATIONS USING CONVOLUTION AND ITERATIVE METHODS
    9.
    发明申请
    THERMAL SIMULATIONS USING CONVOLUTION AND ITERATIVE METHODS 审中-公开
    使用变换和迭代方法的热模拟

    公开(公告)号：US20160092616A1

    公开(公告)日：2016-03-31

    申请号：US14502752

    申请日：2014-09-30

    Applicant: QUALCOMM Incorporated

    Inventor： Ryan Michael Coutts ,  Arpit Mittal ,  Rajat Mittal ,  Mohamed Waleed Allam ,  Mehdi Saeidi

    IPC: G06F17/50 ,  G06F17/15

    CPC classification number: G06F17/5009 ,  G06F17/15 ,  G06F17/5068 ,  G06F2217/78 ,  G06F2217/80

    Abstract: Systems and methods for performing thermal simulations of a system are disclosed herein in. In one embodiment, a computer-implemented method for thermal simulation comprises determining a leakage power profile for a circuit in the system, adding the leakage power profile to a dynamic power profile of the circuit to obtain a combined power profile, and convolving the combined power profile with an impulse response to obtain a thermal response at a location on the system.

    Abstract translation: 用于执行系统的热仿真的系统和方法在本文中公开。在一个实施例中，用于热仿真的计算机实现的方法包括确定系统中的电路的泄漏功率分布，将泄漏功率分布添加到动态功率分布 以获得组合的功率曲线，以及将组合的功率曲线与脉冲响应进行卷积以在系统上的位置处获得热响应。

    DYNAMIC CLOCK AND VOLTAGE SCALING WITH LOW-LATENCY SWITCHING
    10.
    发明申请
    DYNAMIC CLOCK AND VOLTAGE SCALING WITH LOW-LATENCY SWITCHING 有权
    动态时钟和低电平切换低电平切换

    公开(公告)号：US20150227185A1

    公开(公告)日：2015-08-13

    申请号：US14177073

    申请日：2014-02-10

    Applicant: QUALCOMM Incorporated

    Inventor： Dipti Ranjan Pal ,  Paul Ivan Penzes ,  Mohamed Waleed Allam

    IPC: G06F1/32

    CPC classification number: G06F1/3203 ,  G06F1/08 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  H03L7/22 ,  Y02D10/126 ,  Y02D10/152

    Abstract: Systems and methods for dynamic clock and voltage scaling can switch integrated circuits between frequency-voltage modes with low latency. These systems include a resource power manager that can control a power management integrated circuit (PMIC), phase locked loops (PLLs), and clock dividers. The resource power manager controls transitions between frequency-voltage modes. The systems and methods provide dynamic clock and voltage scaling where the transitions between frequency-voltage modes are an atomic operation. Additionally, the resource power manager can control many modules, for example, clock dividers, in parallel. The invention can, due to lower latency between frequency-voltage modes, can provide improved system performance and reduced system power.

    Abstract translation: 用于动态时钟和电压缩放的系统和方法可以在低电平时间的频率 - 电压模式之间切换集成电路。 这些系统包括能够控制功率管理集成电路（PMIC），锁相环（PLL）和时钟分频器的资源功率管理器。 资源功率管理器控制频率 - 电压模式之间的转换。 系统和方法提供动态时钟和电压缩放，其中频率 - 电压模式之间的转换是原子操作。 此外，资源功率管理器可以并行地控制许多模块，例如时钟分频器。 由于频率 - 电压模式之间的较低延迟，本发明可以提供改进的系统性能并降低系统功率。

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