公开(公告)号：US20230148160A1

公开(公告)日：2023-05-11

申请号：US17522729

申请日：2021-11-09

Applicant: QUALCOMM Incorporated

Inventor： Ramkumar SIVAKUMAR ,  Subbarao Surendra CHAKKIRALA

IPC: H02H9/04 ,  H02H1/00

CPC classification number: H02H9/046 ,  H02H1/0007

Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.

公开(公告)号：US20210158001A1

公开(公告)日：2021-05-27

申请号：US16690285

申请日：2019-11-21

Applicant: QUALCOMM Incorporated

Inventor： Sameer WADHWA ,  Subbarao Surendra CHAKKIRALA ,  Mowen YANG

IPC: G06K9/00

Abstract: Certain aspects of the present disclosure provide techniques for look-ahead column sensing for fast voltage-mode read on ultrasonic sensors. For example, certain aspects are directed to an ultrasonic sensor that generally includes a column line, a pixel having a transistor coupled between a voltage rail and the column line, a receiver circuit, and a first column control circuit coupled between the receiver circuit and the pixel, the first column control circuit being configured to electrically isolate the column line from the receiver circuit during a look-ahead settling phase of the ultrasonic sensor, and electrically couple the column line to the receiver circuit during a sensing phase of the ultrasonic sensor.

公开(公告)号：US20220239226A1

公开(公告)日：2022-07-28

申请号：US17161299

申请日：2021-01-28

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Surendra CHAKKIRALA ,  Sherif GALAL ,  Guoqing MIAO

IPC: H02M3/158 ,  H02M1/088

Abstract: Certain aspects of the present disclosure are directed to an apparatus for voltage regulation. The apparatus generally includes a first switch, an inductive element, the first switch being coupled between a first voltage rail and a first terminal of the inductive element, a second switch coupled between a second voltage rail and the first terminal of the inductive element, a third switch coupled between a second terminal of the inductive element and a reference potential node, and a fourth switch coupled between the second terminal of the inductive element and an output node.

公开(公告)号：US20220224230A1

公开(公告)日：2022-07-14

申请号：US17145831

申请日：2021-01-11

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Surendra CHAKKIRALA

IPC: H02M3/158 ,  H02M1/00 ,  H02M3/157

Abstract: An example power supply circuit includes a boost converter and a feedback control circuit. The boost converter generally includes an inductive element coupled between an input voltage node and a switching node, a first switch coupled between the switching node and a reference potential node, a second switch or a diode coupled between the switching node and an output voltage node. The feedback control circuit has a first input coupled to the output voltage node and has an output coupled to at least a control input of the first switch. The feedback control circuit generally includes a voltage node configured to influence a duty cycle of the boost converter; and a feedforward path coupled to the voltage node and configured to have a voltage signal derived from at least one of an input voltage at the input voltage node or an output signal at the output voltage node.

公开(公告)号：US20230300524A1

公开(公告)日：2023-09-21

申请号：US17699902

申请日：2022-03-21

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Surendra CHAKKIRALA ,  Sherif GALAL ,  Earl SCHREYER

IPC: H04R3/00 ,  H02M3/156 ,  H02M1/14

CPC classification number: H04R3/00 ,  H02M3/156 ,  H02M1/14

Abstract: Apparatus and techniques for adaptively adjusting an input current limit for a boost converter supplying power to a load, such as an amplifier. An example circuit for supplying power generally includes a boost converter having an output coupled to a load, and logic configured to adaptively adjust an input current limit for the boost converter based on an estimated output power for the boost converter and to apply the input current limit to the boost converter. One example method for supplying power generally includes converting an input voltage to an output voltage with a boost converter, to power a load for the boost converter, adaptively adjusting an input current limit for the boost converter based on an estimated output power for the boost converter, and applying the input current limit to the boost converter during the converting.

公开(公告)号：US20210234457A1

公开(公告)日：2021-07-29

申请号：US17159082

申请日：2021-01-26

Applicant: QUALCOMM Incorporated

Inventor： Pradeep SILVA ,  Subbarao Surendra CHAKKIRALA ,  Sherif GALAL

IPC: H02M1/32 ,  H02M3/155

Abstract: Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limit circuit comprising a first capacitive element, a charge circuit coupled to the first capacitive element, a first current source, a first resistive element coupled to the first current source, the capacitive element being coupled to a node between the resistive element and the first current source, a sample-and-hold circuit coupled to the first capacitive element, and a clamp circuit coupled between the sample-and-hold circuit and the feedback path.

公开(公告)号：US20180337637A1

公开(公告)日：2018-11-22

申请号：US15598389

申请日：2017-05-18

Applicant: QUALCOMM INCORPORATED

Inventor： Sherif GALAL ,  Subbarao Surendra CHAKKIRALA ,  Khaled ABDELFATTAH ,  Earl SCHREYER

IPC: H03F1/02 ,  H03F3/185 ,  H03F3/217 ,  H04R3/04

CPC classification number: H03F1/0216 ,  H03F1/0233 ,  H03F3/181 ,  H03F3/185 ,  H03F3/217 ,  H03F3/2175 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2200/504 ,  H03F2200/555 ,  H04R3/04

Abstract: An amplifier circuit includes an amplifier and a voltage boost circuit configured to provide a variable supply voltage to the amplifier, the variable supply voltage continuously proportional to an audio input signal, the variable supply voltage configured to follow an output of the amplifier.

公开(公告)号：US20240322685A1

公开(公告)日：2024-09-26

申请号：US18189120

申请日：2023-03-23

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Surendra CHAKKIRALA ,  Dongyang TANG

IPC: H02M3/158 ,  H04R3/00

CPC classification number: H02M3/158 ,  H04R3/00

Abstract: Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to power supply circuit. The power supply circuit may include at least one voltage supply selectively coupled to an output node of the power supply circuit, and a boost converter having: an inductive element coupled to a power source and a switching node; a first transistor coupled between the switching node and a reference potential node; a second transistor having a drain coupled to the switching node; and a third transistor having a source coupled to a source of the second transistor, a drain of the third transistor being coupled to the output node.

公开(公告)号：US20230253934A1

公开(公告)日：2023-08-10

申请号：US17649967

申请日：2022-02-04

Applicant: QUALCOMM Incorporated

Inventor： Subbarao Surendra CHAKKIRALA ,  Sherif GALAL ,  Earl SCHREYER

IPC: H03F3/217 ,  H03F1/02

CPC classification number: H03F3/2175 ,  H03F1/0227 ,  H03F2200/03

Abstract: A hybrid class-H/predictive class-G switching amplifier architecture and techniques for amplifying a signal (e.g., an audio signal) using such an architecture. One example method of amplification generally includes delaying an input signal to generate a delayed version of the input signal, amplifying the delayed version of the input signal with an amplifier powered by a boost converter, and selectively controlling the boost converter to operate in at least one of a predictive class-G mode or a class-H mode, based on a magnitude of the input signal.

公开(公告)号：US20230058434A1

公开(公告)日：2023-02-23

申请号：US17404862

申请日：2021-08-17

Applicant: QUALCOMM Incorporated

Inventor： ChienChung YANG ,  Dongyang TANG ,  Sherif GALAL ,  Xinwang ZHANG ,  Subbarao Surendra CHAKKIRALA ,  Pradeep SILVA

IPC: H03F1/32 ,  H03F3/217

Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.