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公开(公告)号：US20230238925A1
公开(公告)日：2023-07-27
申请号：US17648958
申请日：2022-01-26
Applicant: QUALCOMM Incorporated
Inventor： Dongyang TANG , Xinwang ZHANG , ChienChung YANG , Earl SCHREYER , Sherif GALAL
IPC: H03F3/217
CPC classification number: H03F3/217 , H03F2200/03
Abstract: Aspects of the present disclosure relate to apparatus and methods for dynamically adjusting the common-mode input signal of a power amplifier, such as a class-D power amplifier. One example power amplifier circuit generally includes a first amplifier having a signal input and a power input; and a common-mode adjustment circuit having a first input coupled to the power input of the first amplifier, having an output coupled to the signal input of the first amplifier, and being configured to generate a common-mode signal to apply to the signal input of the first amplifier, based on a power supply voltage on the power input of the first amplifier.
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公开(公告)号：US20230137935A1
公开(公告)日：2023-05-04
申请号：US18146832
申请日：2022-12-27
Applicant: QUALCOMM Incorporated
Inventor： Ramkumar SIVAKUMAR , Jingxue LU , Sherif GALAL , Xinwang ZHANG , Kshitij YADAV
Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for voltage-to-current conversion. For example, certain aspects provide a circuit for signal amplification including a first amplifier; a first transistor, a gate of the first transistor being coupled to an output of the first amplifier and a drain of the first transistor being coupled to an output node of circuit; a first resistive element coupled between a first input node of the circuit and an input of the first amplifier; a second amplifier; a second transistor, a gate of the second transistor being coupled to an output of the second amplifier and a drain of the second transistor being coupled to the output node of circuit; and a second resistive element coupled between a second input node of the circuit and an input of the second amplifier.
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公开(公告)号：US20220239226A1
公开(公告)日：2022-07-28
申请号：US17161299
申请日：2021-01-28
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Surendra CHAKKIRALA , Sherif GALAL , Guoqing MIAO
Abstract: Certain aspects of the present disclosure are directed to an apparatus for voltage regulation. The apparatus generally includes a first switch, an inductive element, the first switch being coupled between a first voltage rail and a first terminal of the inductive element, a second switch coupled between a second voltage rail and the first terminal of the inductive element, a third switch coupled between a second terminal of the inductive element and a reference potential node, and a fourth switch coupled between the second terminal of the inductive element and an output node.
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公开(公告)号：US20210232169A1
公开(公告)日：2021-07-29
申请号：US17143382
申请日：2021-01-07
Applicant: QUALCOMM Incorporated
Inventor： Kshitij YADAV , Sherif GALAL
Abstract: In certain aspects, a clamp circuit includes a first current mirror having a first branch and a second branch, wherein the first current mirror is configured to mirror a current flowing through the first branch of the first current mirror to the second branch of the first current mirror. The clamp circuit also includes a second current mirror having a first branch and a second branch, wherein the second current mirror is configured to mirror a current flowing through the first branch of the second current mirror to the second branch of the second current mirror. The first branch of the first current mirror is coupled in series with the second branch of the second current mirror, and the second branch of the first current mirror is coupled in series with the first branch of the second current mirror.
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公开(公告)号：US20230300524A1
公开(公告)日：2023-09-21
申请号：US17699902
申请日：2022-03-21
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Surendra CHAKKIRALA , Sherif GALAL , Earl SCHREYER
Abstract: Apparatus and techniques for adaptively adjusting an input current limit for a boost converter supplying power to a load, such as an amplifier. An example circuit for supplying power generally includes a boost converter having an output coupled to a load, and logic configured to adaptively adjust an input current limit for the boost converter based on an estimated output power for the boost converter and to apply the input current limit to the boost converter. One example method for supplying power generally includes converting an input voltage to an output voltage with a boost converter, to power a load for the boost converter, adaptively adjusting an input current limit for the boost converter based on an estimated output power for the boost converter, and applying the input current limit to the boost converter during the converting.
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Patent Agency Ranking
公开(公告)号：US20210234457A1
公开(公告)日：2021-07-29
申请号：US17159082
申请日：2021-01-26
Applicant: QUALCOMM Incorporated
Inventor： Pradeep SILVA , Subbarao Surendra CHAKKIRALA , Sherif GALAL
Abstract: Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limit circuit comprising a first capacitive element, a charge circuit coupled to the first capacitive element, a first current source, a first resistive element coupled to the first current source, the capacitive element being coupled to a node between the resistive element and the first current source, a sample-and-hold circuit coupled to the first capacitive element, and a clamp circuit coupled between the sample-and-hold circuit and the feedback path.
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7.发明申请公开(公告)号：US20180337637A1
公开(公告)日：2018-11-22
申请号：US15598389
申请日：2017-05-18
Applicant: QUALCOMM INCORPORATED
Inventor： Sherif GALAL , Subbarao Surendra CHAKKIRALA , Khaled ABDELFATTAH , Earl SCHREYER
CPC classification number: H03F1/0216 , H03F1/0233 , H03F3/181 , H03F3/185 , H03F3/217 , H03F3/2175 , H03F2200/03 , H03F2200/351 , H03F2200/504 , H03F2200/555 , H04R3/04
Abstract: An amplifier circuit includes an amplifier and a voltage boost circuit configured to provide a variable supply voltage to the amplifier, the variable supply voltage continuously proportional to an audio input signal, the variable supply voltage configured to follow an output of the amplifier.
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公开(公告)号：US20230253934A1
公开(公告)日：2023-08-10
申请号：US17649967
申请日：2022-02-04
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Surendra CHAKKIRALA , Sherif GALAL , Earl SCHREYER
CPC classification number: H03F3/2175 , H03F1/0227 , H03F2200/03
Abstract: A hybrid class-H/predictive class-G switching amplifier architecture and techniques for amplifying a signal (e.g., an audio signal) using such an architecture. One example method of amplification generally includes delaying an input signal to generate a delayed version of the input signal, amplifying the delayed version of the input signal with an amplifier powered by a boost converter, and selectively controlling the boost converter to operate in at least one of a predictive class-G mode or a class-H mode, based on a magnitude of the input signal.
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公开(公告)号：US20230058434A1
公开(公告)日：2023-02-23
申请号：US17404862
申请日：2021-08-17
Applicant: QUALCOMM Incorporated
Inventor： ChienChung YANG , Dongyang TANG , Sherif GALAL , Xinwang ZHANG , Subbarao Surendra CHAKKIRALA , Pradeep SILVA
Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.
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公开(公告)号：US20220302884A1
公开(公告)日：2022-09-22
申请号：US17805307
申请日：2022-06-03
Applicant: QUALCOMM Incorporated
Inventor： Khaled Mahmoud ABDELFATTAH ALY , Sherif GALAL , Xin FAN
Abstract: Certain aspects of the present disclosure are generally directed to circuitry and techniques for current sensing. For example, certain aspects provide a circuit for signal amplification including a first amplifier, a second amplifier, and a third amplifier. The circuit also includes a first capacitive element coupled between a first output of the first amplifier and a first input of the third amplifier, a second capacitive element coupled between a second output of the first amplifier and a second input of the third amplifier, a third capacitive element coupled between a first output of the second amplifier and the first input of the third amplifier, and a fourth capacitive element coupled between a second output of the second amplifier and the second input of the third amplifier.
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