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公开(公告)号：US11424672B2
公开(公告)日：2022-08-23
申请号：US17159082
申请日：2021-01-26
Applicant: QUALCOMM Incorporated
Inventor： Pradeep Silva , Subbarao Surendra Chakkirala , Sherif Galal
Abstract: Certain aspects of the present disclosure provide a power supply circuit. The power supply circuit generally includes: a switched-mode power supply (SMPS) having an inductive element and a first switch coupled to the inductive element; a feedback path coupled between an output of the SMPS and a control input of the first switch; and a current limit circuit comprising a first capacitive element, a charge circuit coupled to the first capacitive element, a first current source, a first resistive element coupled to the first current source, the capacitive element being coupled to a node between the resistive element and the first current source, a sample-and-hold circuit coupled to the first capacitive element, and a clamp circuit coupled between the sample-and-hold circuit and the feedback path.
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公开(公告)号：US11017196B1
公开(公告)日：2021-05-25
申请号：US16690285
申请日：2019-11-21
Applicant: QUALCOMM Incorporated
Inventor： Sameer Wadhwa , Subbarao Surendra Chakkirala , Mowen Yang
Abstract: Certain aspects of the present disclosure provide techniques for look-ahead column sensing for fast voltage-mode read on ultrasonic sensors. For example, certain aspects are directed to an ultrasonic sensor that generally includes a column line, a pixel having a transistor coupled between a voltage rail and the column line, a receiver circuit, and a first column control circuit coupled between the receiver circuit and the pixel, the first column control circuit being configured to electrically isolate the column line from the receiver circuit during a look-ahead settling phase of the ultrasonic sensor, and electrically couple the column line to the receiver circuit during a sensing phase of the ultrasonic sensor.
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公开(公告)号：US11799287B2
公开(公告)日：2023-10-24
申请号：US17522729
申请日：2021-11-09
Applicant: QUALCOMM Incorporated
Inventor： Ramkumar Sivakumar , Subbarao Surendra Chakkirala
CPC classification number: H02H9/046 , H02H1/0007
Abstract: A trigger circuit includes a first capacitor and a second capacitor connected in series, a control device and an output of the trigger circuit. The first capacitor is connected to a first voltage rail and to a common node. The second capacitor is connected to a second voltage rail and to the common node. The control device has a first terminal that is coupled to the common node and a control terminal to receive a control signal. The control signal may be decoupled from transients on the first voltage rail and the second voltage rail. The output of the trigger circuit is coupled to the common node.
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4.发明申请公开(公告)号：US20160126839A1
公开(公告)日：2016-05-05
申请号：US14534034
申请日：2014-11-05
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Surendra Chakkirala , Jiwei Chen
IPC: H02M3/158
CPC classification number: H02M3/158 , H02M3/156 , H02M2001/0012 , H02M2001/0022
Abstract: In one embodiment, a control circuit adjusts a duty cycle of a boost converter and comprises a duty cycle limiter generator configured to receive an input voltage provided to the boost converter and to generate a control signal to be provided to the boost converter for adjusting the duty cycle of the boost converter to control the output voltage of the booster converter in response to the input voltage. In one embodiment, the maximum duty cycle limit generator further generates the maximum duty cycle signal in response to an output voltage of the boost converter.
Abstract translation: 在一个实施例中，控制电路调整升压转换器的占空比，并且包括占空比限制器发生器，其被配置为接收提供给升压转换器的输入电压，并产生要提供给升压转换器的控制信号，以调整占空比 升压转换器的周期，以响应于输入电压来控制升压转换器的输出电压。 在一个实施例中，最大占空比限制发生器还响应于升压转换器的输出电压产生最大占空比信号。
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公开(公告)号：US10944385B1
公开(公告)日：2021-03-09
申请号：US16894534
申请日：2020-06-05
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Surendra Chakkirala , Sherif Galal
Abstract: In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.
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Patent Agency Ranking
6.发明授权公开(公告)号：US10326405B2
公开(公告)日：2019-06-18
申请号：US15598389
申请日：2017-05-18
Applicant: QUALCOMM INCORPORATED
Inventor： Sherif Galal , Subbarao Surendra Chakkirala , Khaled Abdelfattah , Earl Schreyer
Abstract: An amplifier circuit includes an amplifier and a voltage boost circuit configured to provide a variable supply voltage to the amplifier, the variable supply voltage continuously proportional to an audio input signal, the variable supply voltage configured to follow an output of the amplifier.
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公开(公告)号：US20180337680A1
公开(公告)日：2018-11-22
申请号：US15597746
申请日：2017-05-17
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Surendra Chakkirala
IPC: H03K19/003 , H03K19/21 , H03K19/0185 , H03K5/1534
CPC classification number: H03K3/35613 , H03K3/356182 , H03K5/1515 , H03K5/1534
Abstract: Aspects of the disclosure are directed to a level shifter circuit. In accordance with one aspect, the level shifter circuit includes a high voltage device; a latch having a first side and a second side, wherein the latch is tied to a weak pull down to ground; and a pair of current-mirror transistors; wherein a first current-mirror transistor of the pair includes a first input coupled to the first side of the latch and a first output coupled to the high voltage device; and wherein a second current-mirror transistor of the pair includes a second input coupled to the second side of the latch and a second output coupled to the high voltage device.
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公开(公告)号：US11683015B2
公开(公告)日：2023-06-20
申请号：US17404862
申请日：2021-08-17
Applicant: QUALCOMM Incorporated
Inventor： ChienChung Yang , Dongyang Tang , Sherif Galal , Xinwang Zhang , Subbarao Surendra Chakkirala , Pradeep Silva
CPC classification number: H03F1/3205 , H03F3/2173 , H03F2200/03 , H03F2200/165 , H03F2200/351
Abstract: A class-D amplifier including a pulse width modulator including an input configured to receive a first signal based on an input signal, and an output configured to generate a pulse width modulated (PWM) signal; an H-bridge including an input coupled to an output of the pulse width modulator and an output coupled to a load, wherein the H-bridge is configured to generate an output signal across the load based on the PWM signal; and a deadtime compensation circuit coupled to the H-bridge, wherein the deadtime compensation circuit is configured to compensate for deadtime distortion in the output signal. The deadtime compensation circuit may be a feedback circuit between an output of the H-bridge and an input of the pulse width modulator, a pulse modification circuit at the output of the pulse width modulator, or an offset signal generating circuit providing an offset signal to the pulse width modulator.
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公开(公告)号：US11275919B2
公开(公告)日：2022-03-15
申请号：US16696371
申请日：2019-11-26
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Surendra Chakkirala , Sameer Wadhwa
IPC: G06K9/20 , G06K9/00 , H03K17/687
Abstract: Certain aspects of the present disclosure provide apparatus and techniques for capacitance modulation to mitigate pixel leakage in ultrasonic sensors. For example, certain aspects are directed to an ultrasonic sensor including a column line, a pixel having a transistor coupled to the column line, a pixel control circuit coupled to a drain the transistor of the pixel. The ultrasonic sensor may also include a column control circuit coupled to a source of the transistor, wherein at least one of the pixel control circuit or the column control circuit is configured to couple at least one of the drain or the source of the transistor, respectively, to an electric ground during a hold phase of the ultrasonic sensor, and a receiver circuit coupled to the column line.
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公开(公告)号：US10374514B2
公开(公告)日：2019-08-06
申请号：US14534034
申请日：2014-11-05
Applicant: QUALCOMM Incorporated
Inventor： Subbarao Surendra Chakkirala , Jiwei Chen
Abstract: In one embodiment, a control circuit adjusts a duty cycle of a boost converter and comprises a duty cycle limiter generator configured to receive an input voltage provided to the boost converter and to generate a control signal to be provided to the boost converter for adjusting the duty cycle of the boost converter to control the output voltage of the booster converter in response to the input voltage. In one embodiment, the maximum duty cycle limit generator further generates the maximum duty cycle signal in response to an output voltage of the boost converter.
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