公开(公告)号：US20210072778A1

公开(公告)日：2021-03-11

申请号：US16561839

申请日：2019-09-05

Applicant: QUALCOMM Incorporated

Inventor： Yue CHAO ,  Marco ZANUSO ,  Rajagopalan RANGARAJAN ,  Yiwu TANG

IPC: G05F1/575 ,  G05F1/595 ,  H03F3/45

Abstract: Certain aspects of the present disclosure provide a low drop-out (LDO) regulator. The LDO regulator generally includes a first p-type metal-oxide-semiconductor transistor (PMOS) having a drain coupled to an output node of the LDO regulator, a first amplifier having an input coupled to a reference voltage node and an output coupled to a gate of the first PMOS transistor, a second PMOS transistor having a source coupled to the output node, and a second amplifier having an input coupled to the output node and an output coupled to a gate of the second PMOS transistor.

公开(公告)号：US20200091866A1

公开(公告)日：2020-03-19

申请号：US16132731

申请日：2018-09-17

Applicant: QUALCOMM INCORPORATED

Inventor： Yue CHAO ,  Yinghan WANG ,  Marco ZANUSO ,  Rajagopalan RANGARAJAN

IPC: H03B5/12 ,  H03L7/093

Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.

公开(公告)号：US20240106442A1

公开(公告)日：2024-03-28

申请号：US17934654

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jianjun YU ,  Yue CHAO ,  Tomas O'SULLIVAN ,  Lai Kan LEUNG

IPC: H03L7/099 ,  H03B5/12 ,  H03K3/0231 ,  H03M1/46

CPC classification number: H03L7/099 ,  H03B5/1293 ,  H03K3/0231 ,  H03M1/46

Abstract: Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.

公开(公告)号：US20210044253A1

公开(公告)日：2021-02-11

申请号：US17076998

申请日：2020-10-22

Applicant: QUALCOMM INCORPORATED

Inventor： Yue CHAO ,  Yinghan WANG ,  Marco ZANUSO ,  Rajagopalan RANGARAJAN

IPC: H03B5/12 ,  H03L7/093 ,  H03L7/08

Abstract: A voltage controlled oscillator (VCO) and buffer circuit includes a voltage controlled oscillator (VCO), a buffer circuit configured to receive a signal generated by the VCO, the buffer circuit comprising a first transistor having a parasitic gate-source capacitance (Cgs), and a second transistor coupled across the first transistor, wherein a gate of the first transistor is coupled to a drain and a source of the second transistor, and a gate of the second transistor is coupled to a source of the first transistor.