公开(公告)号：US20250038752A1

公开(公告)日：2025-01-30

申请号：US18783547

申请日：2024-07-25

Applicant: QUALCOMM Incorporated

Inventor： Jang Joon LEE ,  Aleksandar Miodrag TASIC ,  Prakash THOPPAY EGAMBARAM ,  Kyle David HOLLAND ,  Chih-Fan LIAO ,  Tomas O'SULLIVAN ,  Dhon-Gue LEE ,  Dongling PAN ,  Chirag Dipak PATEL ,  Yangchuan CHEN

IPC: H03L7/099 ,  H03L7/10

Abstract: Certain aspects of the present disclosure are directed towards apparatus and techniques for receiver calibration. An example apparatus generally includes: a first receiver having a first oscillating signal generation circuit, an output of the first oscillating signal generation circuit being coupled to an input of a first splitter, wherein the first splitter has multiple outputs; a second receiver having a second oscillating signal generation circuit coupled to an LO input of each of a first plurality of mixers of the second receiver; and signal paths between the multiple outputs of the first splitter and signal inputs of the first plurality of mixers, respectively.

公开(公告)号：US20240106442A1

公开(公告)日：2024-03-28

申请号：US17934654

申请日：2022-09-23

Applicant: QUALCOMM Incorporated

Inventor： Jianjun YU ,  Yue CHAO ,  Tomas O'SULLIVAN ,  Lai Kan LEUNG

IPC: H03L7/099 ,  H03B5/12 ,  H03K3/0231 ,  H03M1/46

CPC classification number: H03L7/099 ,  H03B5/1293 ,  H03K3/0231 ,  H03M1/46

Abstract: Methods and apparatus for storing a control voltage of a phased-locked loop (PLL) when switching from mission mode to standby mode for the PLL, and for restoring the control voltage of the PLL when switching back to mission mode. An example PLL circuit includes a charge pump, a voltage-controlled oscillator (VCO) having a control input coupled to an output of the charge pump via a node, and a tracking circuit coupled to the node. The tracking circuit is generally configured to sample a voltage of the node during a mission mode, save a representation of the sampled voltage before entering a standby mode, and restore the sampled voltage to the node for reentering the mission mode using the saved representation of the sampled voltage.

公开(公告)号：US20240097689A1

公开(公告)日：2024-03-21

申请号：US17933327

申请日：2022-09-19

Applicant: QUALCOMM Incorporated

Inventor： Jianjun YU ,  Tomas O'SULLIVAN ,  Razak HOSSAIN ,  Lai Kan LEUNG

IPC: H03L7/197 ,  H04L7/033

CPC classification number: H03L7/1976 ,  H04L7/033

Abstract: Aspects of the present disclosure provide techniques and apparatus for synchronizing phase-locked loop (PLL) circuits. An example method of operating PLL circuits includes obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit; and performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication.

公开(公告)号：US20220393565A1

公开(公告)日：2022-12-08

申请号：US17340953

申请日：2021-06-07

Applicant: QUALCOMM Incorporated

Inventor： Alvin Siu-Chi LI ,  Tomas O'SULLIVAN ,  Jianjun YU ,  Yiwu TANG

IPC: H02M1/00 ,  H02M1/084

Abstract: An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.