公开(公告)号：US20190095295A1

公开(公告)日：2019-03-28

申请号：US15713557

申请日：2017-09-22

Applicant: QUALCOMM Incorporated

Inventor： Fahad AHMED ,  Chulmin JUNG ,  Sei Seung YOON ,  Esin TERZIOGLU

IPC: G06F11/20

Abstract: In an example, a method of memory repair may include receiving, by a memory repair unit, a plurality of memory identifiers. The method may include determining, by the memory repair unit, that a first memory identifier of the plurality of memory identifiers corresponds to a first memory of a plurality of memories. The method may include determining, by the memory repair unit, that a second memory identifier corresponds to a second memory of the plurality of memories. The method may include outputting, by the memory repair unit, in parallel: a first value to a repair enable input of the first memory, and a second value to a repair enable input of the second memory.

公开(公告)号：US20150028495A1

公开(公告)日：2015-01-29

申请号：US14338229

申请日：2014-07-22

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong CHEN ,  Ohsang KWON ,  Esin TERZIOGLU ,  Hadi BUNNALIM

IPC: H01L23/528 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L23/498 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An SOC apparatus includes a plurality of gate interconnects with a minimum pitch g, a plurality of metal interconnects with a minimum pitch m, and a plurality of vias interconnecting the gate interconnects and the metal interconnects. The vias have a minimum pitch v. The values m, g, and v are such that g2+m2≧V2 and an LCM of g and m is less than 20 g. The SOC apparatus may further include a second plurality of metal interconnects with a minimum pitch of m2, where m2>m and the LCM of g, m, and m2 is less than 20 g.

Abstract translation: SOC装置包括具有最小间距g的多个栅极互连，具有最小间距m的多个金属互连以及互连栅极互连和金属互连的多个通孔。 通孔具有最小间距v。值m，g和v使得g2 +m2≥V2，g和m的LCM小于20g。 SOC装置还可以包括具有最小间距m2的第二多个金属互连，其中m2> m且g，m和m2的LCM小于20g。

公开(公告)号：US20150301973A1

公开(公告)日：2015-10-22

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern RIM ,  Stanley Seungchul SONG ,  Xiangdong CHEN ,  Raymond George Stephany ,  John Jianhong ZHU ,  Ohsang KWON ,  Esin TERZIOGLU ,  Choh Fei YEAP

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

Abstract translation: 设计导电互连的方法包括至少部分地基于互连迹线间距和指定单元高度的整数倍来确定残余间隔值。 该方法还包括将剩余间隔分配到互连迹线间距内的至少一个互连迹线宽度或互连迹线空间。