公开(公告)号：US20150137879A1

公开(公告)日：2015-05-21

申请号：US14082077

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Hui William Song ,  Mohamed Hassan Abu-Rahma ,  Esin Terizioglu

IPC: G05F5/00

CPC classification number: G05F5/00 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/172

Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.

Abstract translation: 一种用于基于诸如与生成数据相关联的时间延迟等性能来控制提供给数据生成电路的电力的装置和方法。 该装置包括：多个数据产生电路，被配置为响应于第一信号在相应的输出端产生数据; 多个定时电路，被配置为产生与在所述数据生成之间产生数据的所述第一信号与所述数据产生电路的各个输出端的数据出现之间的时间延迟有关的多个第二信号; 电源电路，被配置为产生用于向所述数据产生电路供电的电压; 功率控制器，被配置为基于所述多个第二信号来控制由所述电源电路产生的电压; 以及串行数据传送电路，被配置为将来自各个定时电路的多个第二信号串行传送到功率控制器。

公开(公告)号：US09092013B2

公开(公告)日：2015-07-28

申请号：US14029699

申请日：2013-09-17

Applicant: QUALCOMM Incorporated

Inventor： Hui William Song ,  Mohamed Hassan Abu-Rahma

IPC: H03M1/12 ,  G04F10/00 ,  H03M1/00 ,  H03K5/135 ,  H03L7/081 ,  H04M1/50 ,  H03H11/26

CPC classification number: G04F10/005 ,  H03H11/265 ,  H03K5/135 ,  H03L7/0814 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233 ,  H04M1/505

Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.

Abstract translation: 提供了具有改进的抗亚稳性的时间 - 数字转换器（TDC）。 TDC包括由起始信号选通的环形振荡器。 停止信号触发使用主从触发器捕获来自环形振荡器的相位信号的值。 来自触发器的两个主级的信号被逻辑地组合以产生使计数器计数的计数器时钟信号。 触发器和计数器的输出被编码以产生开始信号和停止信号的转变之间的时间的数字表示。 由于来自触发器的主级的信号被停止信号捕获（并停止切换），所以计数器时钟信号停止翻转，并且计数器停止计数。 这确保捕获的相位信号和计数器的值是一致的，并且避免可能发生的亚稳态误差。

公开(公告)号：US09052725B1

公开(公告)日：2015-06-09

申请号：US14082077

申请日：2013-11-15

Applicant: QUALCOMM Incorporated

Inventor： Hui William Song ,  Mohamed Hassan Abu-Rahma ,  Esin Terizioglu

IPC: G05F5/00 ,  G06F1/32

CPC classification number: G05F5/00 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/172

Abstract: An apparatus and method for controlling power supplied to data generating circuits based on performance, such as time delay associated with generating data. The apparatus includes a plurality of data generating circuits configured to generate data at respective outputs in response to a first signal; a plurality of timing circuits configured to generate a plurality of second signals related to time delays between the first signal initiating the generation of the data and an appearance of the data at the respective outputs of the data generating circuits; a power supply circuit configured to generate a voltage for supplying power to the data generating circuits; a power controller configured to control the voltage generated by the power supply circuit based on the plurality of second signals; and a serial data transfer circuit configured to serial transfer the plurality of second signals from the respective timing circuits to the power controller.

Abstract translation: 一种用于基于诸如与生成数据相关联的时间延迟等性能来控制提供给数据生成电路的电力的装置和方法。 该装置包括：多个数据产生电路，被配置为响应于第一信号在相应的输出端产生数据; 多个定时电路，被配置为产生与在所述数据生成之间产生数据的所述第一信号与所述数据产生电路的各个输出端的数据出现之间的时间延迟有关的多个第二信号; 电源电路，被配置为产生用于向所述数据产生电路供电的电压; 功率控制器，被配置为基于所述多个第二信号来控制由所述电源电路产生的电压; 以及串行数据传送电路，被配置为将来自各个定时电路的多个第二信号串行传送到功率控制器。

公开(公告)号：US20150077279A1

公开(公告)日：2015-03-19

申请号：US14029699

申请日：2013-09-17

Applicant: QUALCOMM Incorporated

Inventor： Hui William Song ,  Mohamed Hassan Abu-Rahma

IPC: H03M1/12

CPC classification number: G04F10/005 ,  H03H11/265 ,  H03K5/135 ,  H03L7/0814 ,  H03M1/00 ,  H03M1/12 ,  H03M2201/4233 ,  H04M1/505

Abstract: Time-to-digital converters (TDC) with improved resistance to metastability are provided. The TDC includes a ring oscillator gated by a start signal. A stop signal triggers capturing values of phase signals from the ring oscillator using master-slave flip-flops. Signals from two of the master stages of the flip-flops are logically combined to produce a counter clock signal that causes a counter to count. The outputs of the flip-flops and of the counter are encoded to produce a digital representation of the time between transitions of the start signal and the stop signal. Since the signals from the master stages of flip-flops are captured (and stop toggling) by the stop signal, the counter clock signal stops toggling, and the counter stops counting. This assures that the values of the captured phase signals and the counter are consistent and avoids metastability errors that could otherwise occur.

Abstract translation: 提供了具有改进的抗亚稳性的时间 - 数字转换器（TDC）。 TDC包括由起始信号选通的环形振荡器。 停止信号触发使用主从触发器捕获来自环形振荡器的相位信号的值。 来自触发器的两个主级的信号被逻辑地组合以产生使计数器计数的计数器时钟信号。 触发器和计数器的输出被编码以产生开始信号和停止信号的转变之间的时间的数字表示。 由于来自触发器的主级的信号被停止信号捕获（并停止切换），所以计数器时钟信号停止翻转，并且计数器停止计数。 这确保捕获的相位信号和计数器的值是一致的，并且避免可能发生的亚稳态误差。