公开(公告)号：US20160006149A1

公开(公告)日：2016-01-07

申请号：US14324067

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Siamak FAZELPOUR ,  Jiantao ZHENG ,  Med NARIMAN

IPC: H01R12/57 ,  H01R43/00 ,  H01R43/16 ,  H01R12/52

CPC classification number: H01R12/57 ,  H01R12/52 ,  H01R12/714 ,  H01R13/2435 ,  H01R13/33 ,  H01R43/007 ,  H01R43/16

Abstract: Methods and apparatuses, wherein the method includes creating a surface mount socket pin for integrated circuit packaging. The method couples a first conductive element to a second conductive element, wherein the closed loop conductor is configured to provide two paths between the first conductive element and second conductive element, wherein a central region of the closed loop conductor is configured to engage with a plurality of symmetrical bumps in a mold to secure the closed loop conductor, wherein the closed loop conductor is elastic.

Abstract translation: 方法和装置，其中所述方法包括创建用于集成电路封装的表面安装插座销。 该方法将第一导电元件耦合到第二导电元件，其中闭环导体被配置为在第一导电元件和第二导电元件之间提供两个路径，其中闭环导体的中心区域被配置为与多个 在模具中的对称凸起以固定闭环导体，其中闭环导体是弹性的。

公开(公告)号：US20160005715A1

公开(公告)日：2016-01-07

申请号：US14324072

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Siamak FAZELPOUR ,  Jiantao ZHENG ,  Mario Francisco VELEZ

IPC: H01L25/065 ,  H01L23/367 ,  H01L25/00

CPC classification number: H01L23/42 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/5385 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19106 ,  H01L2924/3511

Abstract: A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.

Abstract translation: 一种具有设置在基板上的处理器模块和设置在图案化盖上的辅助模块的混合封装。 辅助模块可以是与处理器模块一起位于包装中的存储器模块，电源管理集成电路（PMIC）模块和/或其他合适的模块。 将处理器模块的封装中的辅助模块降低处理器模块和基板之间的焊料凸块处的噪声。 将包含处理器模块的辅助模块也允许将其他模块添加到包装中，而不增加包装的面积。

公开(公告)号：US20160095225A1

公开(公告)日：2016-03-31

申请号：US14497942

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Siamak FAZELPOUR ,  Mario Francisco VELEZ ,  Jiantao ZHENG

IPC: H05K1/18 ,  H01L25/065 ,  H05K3/30 ,  H01L23/498 ,  H01L21/56 ,  H01L23/31 ,  H01L25/00 ,  H01L25/18

CPC classification number: H01L23/49838 ,  H01L23/5227 ,  H01L23/645 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/143 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16195 ,  H05K1/0243 ,  H05K1/0262 ,  H05K2201/1003

Abstract: A semiconductor device includes a first integrated circuit chip, a second integrated circuit chip, a coupled inductor system, and a semiconductor package. The first integrated circuit chip is connected to a substrate and configured to process digital data. The second integrated circuit chip is configured to manage power for the first integrated circuit chip. The coupled inductor system is embedded in the substrate, connected to the second integrated circuit chip, and has a first inductor configured to be magnetically coupled to a second inductor. The semiconductor package is configured to encapsulate the first integrated circuit chip and the second integrated circuit chip.

Abstract translation: 半导体器件包括第一集成电路芯片，第二集成电路芯片，耦合电感器系统和半导体封装。 第一集成电路芯片连接到基板并被配置为处理数字数据。 第二集成电路芯片被配置为管理第一集成电路芯片的电力。 耦合电感器系统被嵌入到基板中，连接到第二集成电路芯片，并且具有被配置为磁耦合到第二电感器的第一电感器。 半导体封装被配置为封装第一集成电路芯片和第二集成电路芯片。