公开(公告)号：US20160093591A1

公开(公告)日：2016-03-31

申请号：US14498965

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey LAN ,  Wenyue ZHANG ,  Yang DU ,  Yong Ju LEE ,  Shiqun GU ,  Jing XIE

IPC: H01L25/065 ,  H01L27/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/683 ,  H01L21/265 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L21/02

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

Abstract translation: 提供了用于制造具有两层或多层的三维集成电路（3D IC）装置的微机电系统（MEMS）键释放结构。 MEMS键释放结构包括可以具有柱或柱结构的MEMS牺牲脱离层，或者替代地，用于粘合和释放的连续牺牲层。

公开(公告)号：US20160261269A1

公开(公告)日：2016-09-08

申请号：US14638270

申请日：2015-03-04

Applicant: QUALCOMM Incorporated

Inventor： Jing XIE ,  Yang DU

IPC: H03K19/00 ,  H03K19/0175 ,  H03K3/037

CPC classification number: H03K19/0021 ,  G06F1/3296 ,  H01L25/0657 ,  H03K3/037 ,  H03K19/017509 ,  Y02D10/172

Abstract: A three-dimensional integrated circuit having a dual or multiple power domain is capable of less energy consumption operation under a given clock rate, which results in an enhanced power-performance-area (PPA) envelope. Sequential logic operates under a system clock that determines the system throughput, whereas combinational logic operates in a different power domain to control overall system power including dynamic and static power. The sequential logic and clock network may be implemented in one tier of the three-dimensional integrated circuit supplied with a relatively high power supply voltage, whereas the combinational logic may be implemented in another tier of the three-dimensional integrated circuit supplied with a relatively low power supply voltage. Further pipeline reorganization may be implemented to leverage the system energy consumption and performance to an optimal point.

Abstract translation: 具有双功率域或多个功率域的三维集成电路在给定的时钟速率下能够更少的能量消耗操作，这导致增强的功率性能面积（PPA）包络。 顺序逻辑在确定系统吞吐量的系统时钟下运行，而组合逻辑在不同的功率域中运行，以控制整个系统功率，包括动态和静态功率。 顺序逻辑和时钟网络可以在被提供有相对高的电源电压的三维集成电路的一个层中实现，而组合逻辑可以在提供有相对低的三维集成电路的另一层中实现 电源电压。 可以实施进一步的管道重组以将系统能量消耗和性能用于最佳点。

公开(公告)号：US20190259677A1

公开(公告)日：2019-08-22

申请号：US16135906

申请日：2018-09-19

Applicant: QUALCOMM Incorporated

Inventor： Jon LASITER ,  Ravindra Vaman SHENOY ,  Kambiz SAMADI ,  Jing XIE

IPC: H01L23/29 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L21/02

Abstract: A device comprising a first die, a second die coupled to a first die, and a polymer planarization layer. The second die includes a side portion and a backside portion. The polymer planarization layer is coupled to the first die and the second die such that the polymer planarization layer is coupled to the side portion and the backside portion of the second die. The polymer planarization layer includes an organic polymer. The polymer planarization layer may include a self planarizing material.