公开(公告)号：US20160042110A1

公开(公告)日：2016-02-11

申请号：US14638323

申请日：2015-03-04

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Pratyush KAMAL ,  Yang DU

IPC: G06F17/50

CPC classification number: G06F17/5072

Abstract: A method of designing a multi-tier three-dimensional integrated circuit (3D IC) is provided that allows the use of two-dimensional integrated circuit (2D IC) design tools. When a 2D IC design tool is used, a macro for each of the tiers indicating areas available and unavailable for placement of circuit elements in each tier is created, and the macros are superimposed on one another. Circuit elements to be implemented in the 3D IC, such as logic cells and interconnects, are shrunk and then placed and repopulated on the superimposed macro. The repopulated circuit elements on the superimposed macro are then partitioned into tiers. Monolithic inter-tier via (MIV) placement and tier-to-tier routing are designed to provide electrical connections between circuit elements in different tiers. Power, performance and area (PPA) optimization may also be performed to optimize the 3D IC layout.

Abstract translation: 提供了一种设计多层三维集成电路（3D IC）的方法，其允许使用二维集成电路（2D IC）设计工具。 当使用2D IC设计工具时，会创建每个层级的宏，指示可用和不可用于在每个层中放置电路元件的区域，并且宏彼此叠加。 要在3D IC中实现的电路元件（例如逻辑单元和互连）被收缩，然后放置并重新填充在叠加的宏上。 然后将重叠的宏上的重新填充的电路元素分成几层。 单层跨层通过（MIV）放置和层到层布线被设计为在不同层级的电路元件之间提供电连接。 也可以执行功率，性能和面积（PPA）优化来优化3D IC布局。

公开(公告)号：US20190259677A1

公开(公告)日：2019-08-22

申请号：US16135906

申请日：2018-09-19

Applicant: QUALCOMM Incorporated

Inventor： Jon LASITER ,  Ravindra Vaman SHENOY ,  Kambiz SAMADI ,  Jing XIE

IPC: H01L23/29 ,  H01L21/768 ,  H01L23/48 ,  H01L23/538 ,  H01L21/56 ,  H01L21/02

Abstract: A device comprising a first die, a second die coupled to a first die, and a polymer planarization layer. The second die includes a side portion and a backside portion. The polymer planarization layer is coupled to the first die and the second die such that the polymer planarization layer is coupled to the side portion and the backside portion of the second die. The polymer planarization layer includes an organic polymer. The polymer planarization layer may include a self planarizing material.

公开(公告)号：US20160322331A1

公开(公告)日：2016-11-03

申请号：US14698842

申请日：2015-04-29

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Yang DU

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/528 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/5286 ,  H01L24/05 ,  H01L24/11 ,  H01L24/14 ,  H01L25/50 ,  H01L27/0688 ,  H01L2224/05147 ,  H01L2224/131 ,  H01L2224/32145 ,  H01L2224/73153 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/10253 ,  H01L2924/014 ,  H01L2924/00014

Abstract: Systems and methods relate to power delivery networks (PDNs) for monolithic three-dimensional integrated circuits (3D-ICs). A monolithic 3D-IC includes a first die adjacent to and in contact with power/ground bumps. A second die is stacked on the first die, the second die separated from the power/ground bumps by the first die. One or more bypass power/ground vias and one or more monolithic inter-tier vias (MIVs) are configured to deliver power from the power/ground bumps to the second die.

Abstract translation: 系统和方法涉及用于单片三维集成电路（3D-IC）的功率传递网络（PDN）。 单片3D-IC包括与电源/接地凸块相邻并接触的第一裸片。 第二管芯被堆叠在第一管芯上，第二管芯通过第一管芯与电源/接地凸块分离。 一个或多个旁路电源/接地通孔和一个或多个单层跨层通孔（MIV）被配置为将功率从电源/接地凸块传递到第二管芯。

公开(公告)号：US20160360606A1

公开(公告)日：2016-12-08

申请号：US14732787

申请日：2015-06-08

Applicant: QUALCOMM Incorporated

Inventor： Mehdi SAEIDI ,  Arpit MITTAL ,  Emil RAHIM ,  Rajat MITTAL ,  Kambiz SAMADI

IPC: H05K1/02 ,  G05B15/02 ,  H05K7/20

CPC classification number: H05K1/0203 ,  G05B15/02 ,  H05K1/0209 ,  H05K1/0272 ,  H05K7/20145 ,  H05K7/20172 ,  H05K7/20209 ,  H05K2201/064

Abstract: Methods and apparatus for implementing a synthetic jet to cool a device are provided. Examples of the techniques keep a device case cool enough to be hand-held, while allowing a higher temperature of a circuit component located in the case, to maximize circuit performance. In an example, provided is a mobile device including a synthetic jet configured to transfer heat within the mobile device. The synthetic jet can be embedded in a circuit board inside the mobile device such that the circuit board defines at least a portion of a chamber of the synthetic jet and defines an orifice of the synthetic jet. The device case can define at least one fluid channel inside the mobile device. Also, the circuit board can define a synthetic jet outlet configured to direct a fluid at the at least one fluid channel. Also provided are methods for controlling a synthetic jet.

Abstract translation: 提供了用于实施合成射流以冷却装置的方法和装置。 这些技术的示例使得器件的壳体足够冷却成为手持式，同时允许位于壳体中的电路元件的较高温度以最大化电路性能。 在一个示例中，提供了包括被配置为在移动设备内传递热量的合成射流的移动设备。 合成射流可以嵌入在移动装置内的电路板中，使得电路板限定合成射流的室的至少一部分并且限定合成射流的孔口。 设备壳体可以在移动设备内定义至少一个流体通道。 此外，电路板可以限定配置成在至少一个流体通道处引导流体的合成射流出口。 还提供了用于控制合成射流的方法。

公开(公告)号：US20160232271A1

公开(公告)日：2016-08-11

申请号：US14617896

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Yang DU

IPC: G06F17/50

CPC classification number: G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L27/0688

Abstract: An intellectual property (IP) block design methodology for three-dimensional (3D) integrated circuits may comprise folding at least one two-dimensional (2D) block that has one or more circuit components into a 3D block that has multiple tiers, wherein the one or more circuit components in the folded 2D block may be distributed among the multiple tiers in the 3D block. Furthermore, one or more pins may be duplicated across the multiple tiers in the 3D block and the one or more duplicated pins may be connected to one another using one or more intra-block through-silicon-vias (TSVs) placed inside the 3D block.

Abstract translation: 用于三维（3D）集成电路的知识产权（IP）块设计方法可以包括将具有一个或多个电路组件的至少一个二维（2D）块折叠到具有多个层的3D块中，其中， 折叠的2D块中的多个电路组件可以分布在3D块中的多个层中。 此外，一个或多个引脚可以跨越3D块中的多个层复制，并且一个或多个复制引脚可以使用放置在3D块内部的一个或多个块内穿通硅通孔（TSV）彼此连接 。

公开(公告)号：US20170092558A1

公开(公告)日：2017-03-30

申请号：US14864951

申请日：2015-09-25

Applicant: QUALCOMM Incorporated

Inventor： Arpit MITTAL ,  Mehdi SAEIDI ,  Kambiz SAMADI

IPC: H01L23/34 ,  H01L25/065 ,  H01L23/528 ,  H01L23/367 ,  H01L25/16

CPC classification number: H01L23/34 ,  H01L23/367 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06589 ,  H01L2924/10253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: An integrated circuit includes inter-digital transducers in a silicon die, where the inter-digital transducers are driven to excite phonons in the silicon die to modulate its thermal conductivity. The thermal conductivity may be increased by exciting acoustic phonons in the silicon die, so that heat dissipation is improved, or the thermal conductivity may be decreased by exciting optical phonons so that heat dissipation is reduced. In conjunction with power management, the thermal conductivity is increased or decreased depending upon the power states of various functional units in the silicon die and depending upon various temperature sensors.

公开(公告)号：US20160233134A1

公开(公告)日：2016-08-11

申请号：US14617901

申请日：2015-02-09

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu LIM ,  Kambiz SAMADI ,  Pratyush KAMAL ,  Yang DU

IPC: H01L21/66 ,  H01L25/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L22/20 ,  H01L22/32 ,  H01L23/5256 ,  H01L23/5382 ,  H01L23/5384 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06596

Abstract: To enable low cost pre-bond testing for a three-dimensional (3D) integrated circuit, a backbone die may have a fully connected two-dimensional (2D) clock tree and one or more non-backbone die may have multiple isolated 2D clock trees. In various embodiments, clock sinks on the backbone die and the non-backbone die can be connected using multiple through-silicon-vias and the isolated 2D clock trees in the non-backbone die can be further connected via a Detachable tree (D-tree), which may comprise a rectilinear minimum spanning tree representing a shortest interconnect among the sinks associated with the 2D clock trees in the non-backbone die. Accordingly, the backbone die and the non-backbone die can be separated and individually tested prior to bonding using one clock probe pad, and the D-tree may be easily removed from the non-backbone die subsequent to the pre-bond testing by burning fuses at the sinks associated with the 2D clock trees.

Abstract translation: 为了实现三维（3D）集成电路的低成本预键测试，主干管芯可以具有完全连接的二维（2D）时钟树，并且一个或多个非主干管芯可以具有多个隔离的2D时钟树 。 在各种实施例中，可以使用多个通硅通孔来连接骨干管芯和非骨干管芯上的时钟汇聚点，并且非骨干管芯中的隔离的2D时钟树可以通过可分离树（D-tree）进一步连接 ），其可以包括表示与非主干管芯中的2D时钟树相关联的汇之间的最短互连的直线最小生成树。 因此，在使用一个时钟探针焊盘进行粘合之前，主骨架和非主干裸片可以被分离和单独测试，并且在通过燃烧进行预键合测试之前，D树可以容易地从非主干模具移除 在与2D时钟树相关联的接收器处保险丝。