公开(公告)号：US20160093591A1

公开(公告)日：2016-03-31

申请号：US14498965

申请日：2014-09-26

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey LAN ,  Wenyue ZHANG ,  Yang DU ,  Yong Ju LEE ,  Shiqun GU ,  Jing XIE

IPC: H01L25/065 ,  H01L27/06 ,  H01L21/762 ,  H01L21/768 ,  H01L21/683 ,  H01L21/265 ,  H01L23/528 ,  H01L23/522 ,  H01L25/00 ,  H01L21/02

CPC classification number: H01L25/0657 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/6835 ,  H01L21/76254 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/8221 ,  H01L23/5226 ,  H01L23/528 ,  H01L25/50 ,  H01L27/0688 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A microelectromechanical system (MEMS) bond release structure is provided for manufacturing of three-dimensional integrated circuit (3D IC) devices with two or more tiers. The MEMS bond release structure includes a MEMS sacrificial release layer which may have a pillar or post structure, or alternatively, a continuous sacrificial layer for bonding and release.

Abstract translation: 提供了用于制造具有两层或多层的三维集成电路（3D IC）装置的微机电系统（MEMS）键释放结构。 MEMS键释放结构包括可以具有柱或柱结构的MEMS牺牲脱离层，或者替代地，用于粘合和释放的连续牺牲层。

公开(公告)号：US20190259780A1

公开(公告)日：2019-08-22

申请号：US16402713

申请日：2019-05-03

Applicant: QUALCOMM Incorporated

Inventor： Shiqun GU ,  Daniel Daeik KIM ,  Matthew Michael NOWAK ,  Jonghae KIM ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  David Francis BERDY

IPC: H01L27/12 ,  H01L23/498 ,  H01L21/306 ,  H01L23/66 ,  H01L27/088 ,  H01L21/304 ,  H01L21/8234 ,  H01L21/84 ,  H01L29/10 ,  H01L27/092 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528

Abstract: An integrated circuit (IC) includes a glass substrate and a buried oxide layer. The IC additionally includes a first semiconductor device coupled to the glass substrate. The first semiconductor device includes a first gate and a first portion of a semiconductive layer coupled to the buried oxide layer. The first gate is located between the glass substrate and the first portion of the semiconductive layer and between the glass substrate and the buried oxide layer. The IC additionally includes a second semiconductor device coupled to the glass substrate. The second semiconductor device includes a second gate and a second portion of the semiconductive layer. The second gate is located between the glass substrate and the second portion of the semiconductive layer. The first portion is discontinuous from the second portion.

公开(公告)号：US20170077093A1

公开(公告)日：2017-03-16

申请号：US15298124

申请日：2016-10-19

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Je-Hsiung Jeffrey LAN ,  Changhan Hobie YUN ,  Jonghae KIM

IPC: H01L27/08 ,  H01L29/93 ,  H01L21/78 ,  H01L29/66

CPC classification number: H01L27/0808 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/78 ,  H01L27/1203 ,  H01L29/66174 ,  H01L29/66181 ,  H01L29/93

Abstract: A symmetric varactor structure may include a first varactor component. The first varactor component may include a gate operating as a second plate, a gate oxide layer operating as a dielectric layer and a body operating as a first plate of an area modulating capacitor. In addition, doped regions may surround the body of the first varactor component. The first varactor component may be supported on a backside by an isolation layer. The symmetric varactor structure may also include a second varactor component electrically coupled to the backside of the first varactor component through a backside conductive layer.

Abstract translation: 对称变容二极管结构可以包括第一变容二极管组件。 第一变容二极管分量可以包括作为第二板操作的栅极，作为电介质层工作的栅极氧化物层和作为区域调制电容器的第一板工作的主体。 此外，掺杂区域可围绕第一变容二极管部件的主体。 第一变容二极管组件可以由隔离层在背面支撑。 对称变容二极管结构还可以包括通过背侧导电层电耦合到第一变容二极管部件的背侧的第二变容二极管部件。

公开(公告)号：US20180083588A1

公开(公告)日：2018-03-22

申请号：US15350969

申请日：2016-11-14

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Shiqun GU ,  Je-Hsiung Jeffrey LAN ,  Jonghae KIM ,  Niranjan Sunil MUDAKATTE ,  David Francis BERDY ,  Mario Francisco VELEZ ,  Chengjie ZUO

IPC: H03H1/00 ,  H01G4/12 ,  H01G4/005 ,  H01G4/40 ,  H03H7/46

CPC classification number: H03H1/00 ,  H01G4/005 ,  H01G4/012 ,  H01G4/1209 ,  H01G4/33 ,  H01G4/40 ,  H01L23/5223 ,  H01L28/60 ,  H03H7/46 ,  H03H7/463 ,  H03H2001/0014 ,  H03H2001/0021 ,  H04B1/0057 ,  H04B1/0458 ,  H04B1/18

Abstract: A capacitor may include a first capacitor plate having a first length. The capacitor may also include an inorganic capacitor dielectric layer on sidewalls and a surface of the first capacitor plate and a second capacitor plate on the inorganic capacitor dielectric layer. The second capacitor plate may have a second length less than the first length of the first capacitor plate. The capacitor may also include a conductive contact landing directly on the first capacitor plate. The conductive contact may land directly on the first capacitor plate by extending through the inorganic capacitor dielectric layer and an organic interlayer dielectric supported by the inorganic capacitor dielectric layer.

公开(公告)号：US20170140862A1

公开(公告)日：2017-05-18

申请号：US14941493

申请日：2015-11-13

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Daeik Daniel KIM ,  Chengjie ZUO ,  Jonghae KIM ,  Je-Hsiung Jeffrey LAN ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE

IPC: H01F10/12 ,  H01F41/04 ,  H01F27/28

CPC classification number: H01F10/12 ,  H01F17/0013 ,  H01F27/2804 ,  H01F41/042 ,  H01F41/046 ,  H01F2017/0066 ,  H01F2027/2809

Abstract: A thin film magnet (TFM) three-dimensional (3D) inductor structure may include a substrate with conductive vias extending through the substrate. The TFM 3D inductor structure may also include a magnetic thin film layer on at least sidewalls of the conductive vias and on a first side and an opposing second side of the substrate. The TFM 3D inductor structure may further include a first conductive trace directly on the magnetic thin film layer on the first side of the substrate and electrically coupling to at least one of the conductive vias. The TFM 3D inductor structure also includes a second conductive trace directly on the magnetic thin film layer on the second side of the substrate and coupled to at least one of the conductive vias.

公开(公告)号：US20170178810A1

公开(公告)日：2017-06-22

申请号：US14976973

申请日：2015-12-21

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Daeik Daniel KIM ,  Niranjan Sunil MUDAKATTE ,  Je-Hsiung Jeffrey LAN ,  Chengjie ZUO ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Jonghae KIM

IPC: H01G4/30 ,  H01G4/01

CPC classification number: H01G4/30 ,  H01G4/01 ,  H01G4/33 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/86 ,  H01L28/87 ,  H01L29/94

Abstract: An exemplary MIM capacitor may include a first metal plate, a dielectric layer on the first metal plate, a second metal plate on the dielectric layer, a via layer on the second metal plate, and a third metal plate on the via layer where the second metal plate has a tapered outline with a first side and a second side longer than the first side such that the second side provides a lower resistance path for a current flow.

公开(公告)号：US20150287677A1

公开(公告)日：2015-10-08

申请号：US14483944

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Je-Hsiung Jeffrey LAN ,  David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L21/283

CPC classification number: H01L23/5227 ,  H01L21/283 ,  H01L21/76877 ,  H01L23/522 ,  H01L23/5222 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L23/5329 ,  H01L27/01 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit device includes a substrate. The integrated circuit device also includes a first conductive stack including a back-end-of-line (BEOL) conductive layer at a first elevation with reference to the substrate. The integrated circuit device also includes a second conductive stack including the BEOL conductive layer at a second elevation with reference to the substrate. The second elevation differs from the first elevation.

Abstract translation: 集成电路器件包括衬底。 集成电路器件还包括第一导电叠层，其包括参考衬底的第一高度处的后端行（BEOL）导电层。 集成电路器件还包括第二导电叠层，其包括相对于衬底的第二高度处的BEOL导电层。 第二个高程与第一个高程不同。

公开(公告)号：US20170084565A1

公开(公告)日：2017-03-23

申请号：US14859323

申请日：2015-09-20

Applicant: QUALCOMM Incorporated

Inventor： Mario Francisco VELEZ ,  David Francis BERDY ,  Changhan Hobie YUN ,  Jonghae KIM ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Je-Hsiung Jeffrey LAN ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA

IPC: H01L23/00

CPC classification number: H01L24/17 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/09 ,  H01L24/11 ,  H01L2224/023 ,  H01L2224/0905

Abstract: An integrated circuit device in a wafer level package (WLP) includes ball grid array (BGA) balls fabricated with cavities filled with adhesives for improved solder joint reliability.

公开(公告)号：US20170077214A1

公开(公告)日：2017-03-16

申请号：US14853967

申请日：2015-09-14

Applicant: QUALCOMM Incorporated

Inventor： Niranjan Sunil MUDAKATTE ,  Daeik Daniel KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Je-Hsiung Jeffrey LAN ,  Chengjie ZUO ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01L49/02

CPC classification number: H01L28/60 ,  H01L23/5223 ,  H01L24/13 ,  H01L27/0805 ,  H01L28/87 ,  H01L28/91 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/13109 ,  H01L2224/94 ,  H01L2924/10329 ,  H01L2924/1033 ,  H01L2924/10337 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2224/03

Abstract: An augmented capacitor structure includes a substrate and a first capacitor plate of a first conductive layer on the substrate. The augmented capacitor structure also includes an insulator layer on a surface of the first capacitor plate facing away from the substrate and a second capacitor plate. The second capacitor plate includes a second conductive layer on the insulator layer, supported by the first capacitor plate as a first capacitor. A second capacitor electrically is coupled in series with the first capacitor. The first capacitor plate is shared by the first capacitor and the second capacitor as a shared first capacitor plate. An extended first capacitor plate includes a first dummy portion of a third conductive layer and a first dummy via bar extending along the surface of the shared first capacitor plate. The first dummy portion extends along and is supported by the first dummy via bar.

Abstract translation: 增强电容器结构包括基板和在基板上的第一导电层的第一电容器板。 增强电容器结构还包括在第一电容器板的远离衬底的表面上的绝缘体层和第二电容器板。 第二电容器板包括在绝缘体层上的第二导电层，由第一电容器板作为第一电容器支撑。 与第一电容器串联耦合的第二电容器。 第一电容器板由第一电容器和第二电容器共享作为共用的第一电容器板。 扩展的第一电容器板包括第三导电层的第一虚拟部分和沿着共享的第一电容器板的表面延伸的第一虚设通孔条。 第一虚拟部分沿第一虚拟通孔条延伸并由第一虚拟通孔支撑。