公开(公告)号：US10291242B1

公开(公告)日：2019-05-14

申请号：US15993254

申请日：2018-05-30

Applicant: QUALCOMM Incorporated

Inventor： Mohammad Elbadry ,  Marco Zanuso ,  Tsai-Pi Hung ,  Francesco Gatta ,  Yunliang Zhu

IPC: H03L7/00 ,  H04B1/04 ,  H03L7/099 ,  H03L7/085 ,  H04L7/033

Abstract: Certain aspects of the present disclosure generally relate to techniques and circuits for phase correction, or at least adjustment, of multiple local-oscillator (LO) signals. For example, certain aspects provide an apparatus for phase adjustment. The apparatus generally includes a phase-locked loop (PLL), at least one frequency divider coupled to an output of the PLL, the at least one first frequency divider being external to the PLL, a phase adjustment circuit having an input coupled to an output of the frequency divider, and at least one mixer having an input coupled to at least one output of the phase adjustment circuit.

公开(公告)号：US09893875B2

公开(公告)日：2018-02-13

申请号：US15270444

申请日：2016-09-20

Applicant: QUALCOMM Incorporated

Inventor： Marco Zanuso ,  Mohammad Elbadry ,  Tsai-Pi Hung ,  Ravi Sridhara ,  Francesco Gatta ,  Jingcheng Zhuang

IPC: H03D3/24 ,  H04L7/033 ,  H04L29/06 ,  H04L5/14 ,  H03L7/14 ,  H03L7/197 ,  H04W84/04

CPC classification number: H04L7/033 ,  H03L7/14 ,  H03L7/143 ,  H03L7/1976 ,  H03L2207/08 ,  H04L5/14 ,  H04L69/28 ,  H04W84/042

Abstract: A phase discontinuity mitigation implementation within a phased lock loop (PLL) improves throughput of a radio access technology. The throughput is improved by maintaining a phase of the PLL while powering off some devices of the PLL, such as a local oscillator (LO) frequency divider. In one instance, when the PLL is powered down, one or more portions of a delta sigma modulator for the PLL are clocked with a reference clock for the PLL. This implementation maintains phase continuity when the first phase lock loop turns back on.