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1.发明申请公开(公告)号：US20130285687A1
公开(公告)日：2013-10-31
申请号：US13793880
申请日：2013-03-11
Applicant: QUALCOMM INCORPORATED
Inventor： Tapan J. Chakraborty , Rajamani Sethuram , Riko Radojcic
IPC: G01R31/28
CPC classification number: G01R31/2874 , G01R31/2856 , G01R31/2875
Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.
Abstract translation: 本文描述了用于通过将结构测试的向量应用于集成电路（IC）来模拟功能测试的热点分布的装置和方法。 然后可以测试和表征热点的影响。 矢量可以在IC上产生，或者可以经由外部源馈送到IC。
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2.发明授权Integrated circuit leakage power reduction using enhanced gated-Q scan techniques 有权使用增强型门控Q扫描技术的集成电路泄漏功率降低公开(公告)号：US09584120B2
公开(公告)日：2017-02-28
申请号：US13887517
申请日：2013-05-06
Applicant: QUALCOMM Incorporated
Inventor： Rajamani Sethuram , Karim Arabi
IPC: H03K19/173 , H03K19/00 , G01R31/3183 , G01R31/3185 , G06F17/50
CPC classification number: H03K19/0008 , G01R31/318342 , G01R31/318575 , G06F17/50 , H03K19/173
Abstract: Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
Abstract translation: 通过确定电路设计的最小泄漏状态，然后选择将电路设计保持在其最低泄漏状态的逻辑门来选择用于Q门控的特定逻辑门。 根据实现最小泄漏状态所需的输入，栅极可以选择为NOR或或门。 在选择的操作模式期间可以启用用于实现最小泄漏状态的门实现的Q门控。 电路的最小泄漏状态可以用自动测试图形生成（ATPG）工具确定。
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3.发明授权Method and apparatus for characterizing thermal marginality in an integrated circuit 有权用于表征集成电路中热边缘度的方法和装置公开(公告)号：US09285418B2
公开(公告)日：2016-03-15
申请号：US13793880
申请日：2013-03-11
Applicant: QUALCOMM Incorporated
Inventor： Tapan J Chakraborty , Rajamani Sethuram , Ratibor Radojcic
CPC classification number: G01R31/2874 , G01R31/2856 , G01R31/2875
Abstract: Apparatus and methods are described herein for emulating the hot spot distribution of a functional test by applying vectors for structural test to an integrated circuit (IC). The affects of the hot spots can then be tested and characterized. The vectors may be generated on the IC, or may be fed to the IC via an external source.
Abstract translation: 本文描述了用于通过将结构测试的向量应用于集成电路（IC）来模拟功能测试的热点分布的装置和方法。 然后可以测试和表征热点的影响。 矢量可以在IC上产生，或者可以经由外部源馈送到IC。
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4.发明申请INTEGRATED CIRCUIT LEAKAGE POWER REDUCTION USING ENHANCED GATED-Q SCAN TECHNIQUES 有权使用增强型GATE-Q扫描技术的集成电路漏电功率降低公开(公告)号：US20130241593A1
公开(公告)日：2013-09-19
申请号：US13887517
申请日：2013-05-06
Applicant: QUALCOMM INCORPORATED
Inventor： Rajamani Sethuram , Karim Arabi
IPC: H03K19/00 , G06F17/50 , H03K19/173
CPC classification number: H03K19/0008 , G01R31/318342 , G01R31/318575 , G06F17/50 , H03K19/173
Abstract: Specific logic gates for Q-gating are selected by determining the minimum leakage state for a circuit design and then selecting logic gates that hold the circuit design in its lowest leakage state. Depending on the input desired to implement the minimum leakage state, the gate may be selected as a NOR or OR gate. Q-gating that is implemented with gates chosen to implement the minimum leakage state may be enabled during selected operating modes. The minimum leakage state of a circuit can be determined with an automatic test pattern generation (ATPG) tool.
Abstract translation: 通过确定电路设计的最小泄漏状态，然后选择将电路设计保持在其最低泄漏状态的逻辑门来选择用于Q门控的特定逻辑门。 根据实现最小泄漏状态所需的输入，栅极可以选择为NOR或或门。 在选择的操作模式期间可以启用用于实现最小泄漏状态的门实现的Q门控。 电路的最小泄漏状态可以用自动测试图形生成（ATPG）工具来确定。
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