公开(公告)号：US10971476B2

公开(公告)日：2021-04-06

申请号：US14254494

申请日：2014-04-16

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/31 ,  H01L23/522 ,  H01L23/00 ,  H05K1/09 ,  H05K1/11 ,  H01L23/498 ,  H01L25/10 ,  H01L21/48 ,  H01L23/538 ,  H01L23/15 ,  H01L23/14

Abstract: A bottom package substrate is provided that includes a plurality of metal posts that electrically couple through a die-side redistribution layer to a plurality of die interconnects. The metal posts and the die interconnects are plated onto a seed layer on the bottom package substrate.

公开(公告)号：US09881859B2

公开(公告)日：2018-01-30

申请号：US14273882

申请日：2014-05-09

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok We ,  Dong Wook Kim ,  Jae Sik Lee ,  Shiqun Gu ,  Ratibor Radojcic

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/522 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L25/065 ,  H01L23/528 ,  H01L21/311 ,  H05K1/09 ,  H05K1/11 ,  H01L25/10 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/49827 ,  H01L21/31127 ,  H01L21/561 ,  H01L21/565 ,  H01L21/78 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/498 ,  H01L23/49866 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5385 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16235 ,  H01L2224/81411 ,  H01L2224/81424 ,  H01L2224/81439 ,  H01L2224/81444 ,  H01L2224/81447 ,  H01L2224/81455 ,  H01L2224/81466 ,  H01L2224/81484 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06548 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/141 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/20648 ,  H01L2924/3511 ,  H05K1/09 ,  H05K1/115 ,  H05K2201/09563 ,  H01L2924/014 ,  H01L2224/81

Abstract: A substrate block is provided that has an increased width. The substrate block comprises two substrate bars, and the substrate bars each comprise a substrate and a plurality of filled vias through the substrate. The substrate block may be used to manufacture package substrates, and these package substrate may be incorporated into a PoP structure. The package substrate includes a carrier having a plurality of vertical interconnections and a bar coupled to the vertical interconnections.

公开(公告)号：US09869713B2

公开(公告)日：2018-01-16

申请号：US14639511

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Ratibor Radojcic ,  Yang Du

IPC: G01R31/02 ,  G01R31/28 ,  G01R19/165 ,  H01L23/48 ,  H01L23/58 ,  H01L23/64 ,  H01L27/06 ,  H01L21/66 ,  G01R31/3185

CPC classification number: G01R31/2851 ,  G01R19/16533 ,  G01R31/2853 ,  G01R31/318513 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/585 ,  H01L23/647 ,  H01L27/0688

Abstract: Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.

公开(公告)号：US09704796B1

公开(公告)日：2017-07-11

申请号：US15041853

申请日：2016-02-11

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Shree Krishna Pandey ,  Ratibor Radojcic

IPC: H01L23/498 ,  H01L23/31 ,  H01L21/48 ,  H01L23/00

CPC classification number: H01L23/49838 ,  H01L21/4846 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/5389 ,  H01L23/642 ,  H01L24/17 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/16268 ,  H01L2224/18 ,  H01L2924/05042 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19102

Abstract: Some features pertain to an integrated device that includes a die and a first redistribution portion coupled to the die. The first redistribution portion includes at least one dielectric layer and a capacitor. The capacitor includes a first plate, a second plate, and an insulation layer located between the first plate and the second plate. The first redistribution portion further includes several first pins coupled to the first plate of the capacitor. The first redistribution portion further includes several second pins coupled to the second plate of the capacitor. In some implementations, the capacitor includes the first pins and/or the second pins. In some implementations, at least one pin from the several first pins traverses through the second plate to couple to the first plate of the capacitor. In some implementations, the second plate comprises a fin design.

公开(公告)号：US20150214127A1

公开(公告)日：2015-07-30

申请号：US14162969

申请日：2014-01-24

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim

IPC: H01L23/367 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L23/367 ,  H01L23/13 ,  H01L23/3677 ,  H01L23/473 ,  H01L23/5389 ,  H01L23/544 ,  H01L24/19 ,  H01L24/32 ,  H01L24/83 ,  H01L2223/54426 ,  H01L2224/04105 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83192 ,  H01L2224/8385 ,  H01L2224/92244 ,  H01L2924/1015 ,  H01L2924/12042 ,  H01L2924/15151 ,  H01L2924/15156 ,  H01L2924/157 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/00

Abstract: Some features pertain to an integrated device that includes a substrate. The substrate includes a first cavity (e.g., trench). The first cavity includes a first edge that is non-vertical. The first cavity is configured to align a die towards a center of the first cavity when the die is placed off-center of the first cavity. The integrated device also includes a first die positioned in the first cavity. The integrated device further includes a redistribution portion coupled to the first die. In some implementations, the first edge is a first wall of the first cavity. In some implementations, the first cavity includes a first opening and a first base portion. The first opening of the first cavity is greater than the first base portion of the first cavity.

Abstract translation: 一些特征涉及包括基板的集成装置。 衬底包括第一腔（例如沟槽）。 第一腔包括非垂直的第一边缘。 第一腔被配置成当模具被放置在第一腔体的中心以下时将模具朝着第一空腔的中心对准。 集成装置还包括位于第一腔中的第一模具。 集成器件还包括耦合到第一管芯的再分配部分。 在一些实施方式中，第一边缘是第一腔的第一壁。 在一些实施方式中，第一腔包括第一开口和第一基部。 第一腔的第一开口大于第一腔的第一基部。

公开(公告)号：US20140225246A1

公开(公告)日：2014-08-14

申请号：US14133451

申请日：2013-12-18

Applicant: QUALCOMM INCORPORATED

Inventor： Brian Matthew Henderson ,  Durodami Joscelyn Lisk ,  Shiqun Gu ,  Ratibor Radojcic ,  Matthew Michael Nowak

IPC: H01L23/538 ,  H01L23/36

CPC classification number: H01L23/5384 ,  H01L21/50 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/36 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/5286 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/19 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17181 ,  H01L2224/73259 ,  H01L2224/92224 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/15184 ,  H01L2924/15311

Abstract: Some implementations provide an integrated device that includes a first substrate, a first die coupled to the first substrate, a second die coupled to the first die, and a second substrate coupled to the second die. The second substrate is configured to provide an electrical path for a signal to the second die. The integrated device further includes a molding surrounding the first die and the second die, and several through mold vias (TMVs) coupled to the second substrate. The TMVs are configured to provide an electrical path for the signal to the second die through the second substrate. In some implementations, the second substrate includes a signal distribution structure configured to provide the electrical path for the signal to the second die. In some implementations, the first substrate and the second substrate are part of a signal distribution network that provides signal to the second die.

Abstract translation: 一些实施方案提供了集成器件，其包括第一衬底，耦合到第一衬底的第一裸片，耦合到第一裸片的第二裸片以及耦合到第二裸片的第二衬底。 第二基板被配置为提供用于到第二管芯的信号的电路径。 集成装置还包括围绕第一管芯和第二管芯的模制件以及耦合到第二衬底的多个通孔模具通孔（TMV）。 TMV被配置为提供通过第二基板的信号到第二管芯的电路径。 在一些实施方案中，第二衬底包括被配置为向第二裸片提供信号的电路的信号分配结构。 在一些实施方案中，第一衬底和第二衬底是向第二裸片提供信号的信号分配网络的一部分。

公开(公告)号：US09853446B2

公开(公告)日：2017-12-26

申请号：US14838034

申请日：2015-08-27

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Eugene Robert Worley ,  Ratibor Radojcic ,  Urmi Ray

IPC: H02H9/04 ,  H01L23/48 ,  H01L23/60 ,  H01L23/62 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L23/48 ,  H01L23/60 ,  H01L23/62 ,  H01L27/0255 ,  H01L27/0292 ,  H01L27/0296 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/181 ,  H02H9/044 ,  H01L2924/00012

Abstract: An intergrated circuit (IC) package includes a die, a package substrate coupled to the die, and a first electrostatic discharge (ESD) protection component coupled to the package substrate, where the first electrostatic discharge (ESD) protection component is configured to provide package level electrostatic discharge (ESD) protection. In some implementations, the first electrostatic discharge (ESD) protection component is embedded in the package substrate. In some implementations, the die includes an internal electrostatic discharge (ESD) protection component configured to provide die level electrostatic discharge (ESD) protection. In some implementations, the internal electrostatic discharge (ESD) protection component and the first electrostatic discharge (ESD) protection component are configured to provide cumulative electrostatic discharge (ESD) protection for the die.

公开(公告)号：US20130316526A1

公开(公告)日：2013-11-28

申请号：US13956703

申请日：2013-08-01

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Yiming Li

IPC: H01L23/62

CPC classification number: H01L23/62 ,  H01L23/29 ,  H01L23/60 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05567 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A voltage-switchable dielectric layer may be employed on a die for electrostatic discharge (ESD) protection. The voltage-switchable dielectric layer functions as a dielectric layer between terminals of the die during normal operation of the die. When ESD events occur at the terminals of the die, a high voltage between the terminals switches the voltage-switchable dielectric layer into a conducting layer to allow current to discharge to a ground terminal of the die without the current passing through circuitry of the die. Thus, damage to the circuitry of the die is reduced or prevented during ESD events on dies with the voltage-switchable dielectric layer. The voltage-switchable dielectric layer may be deposited on the back side of a die for protection during stacking with a second die to form a stacked IC. A method includes depositing a voltage-switchable dielectric layer on a first die between a first terminal and a second terminal.

Abstract translation: 可以在用于静电放电（ESD）保护的管芯上使用电压可切换电介质层。 电压切换介电层在芯片的正常操作期间用作模具的端子之间的介电层。 当在芯片的端子处发生ESD事件时，端子之间的高电压将可切换电压的电介质层切换成导电层，以允许电流放电到裸片的接地端，而不会流过电流通过电路的电路。 因此，在具有可电压切换介电层的管芯上的ESD事件期间，对管芯电路的损坏被减小或防止。 电压可切换电介质层可以沉积在管芯的背面上，用于在与第二管芯堆叠期间进行保护以形成堆叠的IC。 一种方法包括在第一端子和第二端子之间的第一管芯上沉积可电压切换介电层。

公开(公告)号：US20160258996A1

公开(公告)日：2016-09-08

申请号：US14639511

申请日：2015-03-05

Applicant: QUALCOMM Incorporated

Inventor： Sung Kyu Lim ,  Ratibor Radojcic ,  Yang Du

IPC: G01R31/28 ,  H01L27/06 ,  G01R19/165 ,  H01L23/58 ,  H01L23/64 ,  H01L21/66 ,  H01L23/48

CPC classification number: G01R31/2851 ,  G01R19/16533 ,  G01R31/2853 ,  G01R31/318513 ,  H01L22/14 ,  H01L22/34 ,  H01L23/481 ,  H01L23/585 ,  H01L23/647 ,  H01L27/0688

Abstract: Through-silicon via (TSV) crack sensors for detecting TSV cracks in three-dimensional (3D) integrated circuits (ICs) (3DICs), and related methods and systems are disclosed. In one aspect, a TSV crack sensor circuit is provided in which doped rings for a plurality of TSVs are interconnected in parallel such that all interconnected TSV doped rings may be tested at the same time by providing a single current into the contacts of the interconnected doped rings. In another aspect, a TSV crack sensor circuit is provided including one or more redundant TSVs. Each doped ring for a corresponding TSV is tested independently, and a defective TSV may be replaced with a spare TSV whose doped ring is not detected to be cracked. This circuit allows for correction of a compromised 3DIC by replacing possibly compromised TSVs with spare TSVs.

Abstract translation: 公开了用于检测三维（3D）集成电路（IC）（3DIC）中的TSV裂纹的穿通硅通孔（TSV）裂纹传感器以及相关方法和系统。 在一个方面，提供一种TSV裂纹传感器电路，其中用于多个TSV的掺杂环并联互连，使得所有互连的TSV掺杂环可以同时测试，通过向互连的掺杂的触点提供单个电流 戒指。 另一方面，提供包括一个或多个冗余TSV的TSV裂纹传感器电路。 用于对应的TSV的每个掺杂环被独立地测试，并且可以用未检测到其掺杂环被破裂的备用TSV来替换有缺陷的TSV。 该电路允许通过用备用TSV替换可能受损的TSV来校正受损的3DIC。

公开(公告)号：US20150318262A1

公开(公告)日：2015-11-05

申请号：US14324136

申请日：2014-07-04

Applicant: QUALCOMM Incorporated

Inventor： Shiqun Gu ,  Ratibor Radojcic ,  Dong Wook Kim ,  Jae Sik Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L21/568 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3107 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5385 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/92 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/023 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/171 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81895 ,  H01L2224/81896 ,  H01L2224/83005 ,  H01L2224/92125 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01029 ,  H01L2924/1434 ,  H01L2924/1517 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1533 ,  H01L2924/18161 ,  H05K3/4688 ,  H01L2924/014

Abstract: Some novel features pertain to an integrated device (e.g., integrated package) that includes a base portion for the integrated device, a first die (e.g., first wafer level die), and a second die (e.g., second wafer level die). The base portion includes a first inorganic dielectric layer, a first set of interconnects located in the first inorganic dielectric layer, a second dielectric layer different from the first inorganic dielectric layer, and a set of redistribution metal layers in the second dielectric layer. The first die is coupled to a first surface of the base portion. The second die is coupled to the first surface of the base portion, the second die is electrically coupled to the first die through the first set of interconnects.

Abstract translation: 一些新颖的特征涉及集成器件（例如，集成封装），其包括用于集成器件的基底部分，第一管芯（例如，第一晶片级管芯）和第二管芯（例如，第二晶片级管芯）。 基部包括第一无机电介质层，位于第一无机电介质层中的第一组互连，不同于第一无机介电层的第二电介质层和第二介电层中的一组再分布金属层。 第一管芯耦合到基部的第一表面。 第二管芯耦合到基部的第一表面，第二管芯通过第一组互连件电耦合到第一管芯。