公开(公告)号：US20210175152A1

公开(公告)日：2021-06-10

申请号：US16704789

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Chaoqi ZHANG ,  Rajneesh KUMAR ,  Li-Sheng WENG ,  Darryl Sheldon JESSIE ,  Suhyung HWANG ,  Jeahyeong HAN ,  Xiaoming CHEN ,  Jaehyun YEON

IPC: H01L23/48 ,  H01L23/31 ,  H01L21/67 ,  H01L21/56

Abstract: A package that includes a substrate having a routing region and a non-routing region along a periphery of the substrate. The non-routing region includes a plurality of vias configured as a shield. The package includes an integrated device coupled to the substrate, and an encapsulation layer located over the substrate such that the encapsulation layer encapsulates the integrated device.

公开(公告)号：US20160027562A1

公开(公告)日：2016-01-28

申请号：US14340542

申请日：2014-07-24

Applicant: QUALCOMM Incorporated

Inventor： Yuan FENG ,  Kyu-Pyung HWANG ,  Xiaoming CHEN

IPC: H01C17/065 ,  H01C1/012 ,  H01C1/14 ,  H01C7/00

CPC classification number: H01C7/003 ,  H01C17/003 ,  H01C17/06513 ,  H01C17/22 ,  H01C17/24

Abstract: A method of additive tuning a resistor includes measuring resistance across a recessed area of the resistor using at least two terminals, depositing resistance material from an ink jet across the recessed area of the resistor device concurrently with the measuring resistance, and ceasing the depositing upon obtaining a measurement of a resistance threshold value.

Abstract translation: 一种对电阻器进行加法调谐的方法包括使用至少两个端子来测量电阻器的凹陷区域的电阻，在与测量电阻同时地从电阻器件的凹陷区域喷射电阻材料，并且在获得时停止沉积 电阻阈值的测量值。

公开(公告)号：US20150364438A1

公开(公告)日：2015-12-17

申请号：US14303465

申请日：2014-06-12

Applicant: QUALCOMM Incorporated

Inventor： Haiyong XU ,  Manoj Ashok KAKADE ,  Hua GUAN ,  Yue LI ,  Xiaoming CHEN ,  Ruey Kae ZANG

IPC: H01L23/00 ,  B23K3/06

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/11 ,  H01L24/75 ,  H01L2224/1412 ,  H01L2924/15311 ,  H01L2924/301

Abstract: Methods and apparatuses for balancing current delivery. The method couples a low resistance portion of a ball grid array (BGA) to an input portion by at least two vias forming a three-dimensional section. The method couples at least one ball of the BGA to the low resistance portion over a narrow trace.

Abstract translation: 用于平衡当前交付的方法和装置。 该方法通过形成三维截面的至少两个通孔将球栅阵列（BGA）的低电阻部分耦合到输入部分。 该方法将BGA中的至少一个球与窄电阻部分连接。

公开(公告)号：US20220192006A1

公开(公告)日：2022-06-16

申请号：US17122820

申请日：2020-12-15

Applicant: QUALCOMM Incorporated

Inventor： Xiaoming CHEN ,  Darryl Sheldon JESSIE

IPC: H05K1/02 ,  H05K1/11

Abstract: Certain aspects of the present disclosure generally relate to a circuit board with ground vias offset from associated ground bumps. One example circuit board generally includes a first signal connection terminal configured to connect a signal line of the circuit board to an integrated circuit (IC); a ground plane having a first ground connection terminal disposed adjacent to the first signal connection terminal, the first ground connection terminal being configured to provide a ground connection between the ground plane and the IC; and a first ground via associated with and disposed adjacent to the first ground connection terminal and coupled to the ground plane, wherein, from an overhead view of the circuit board, the first ground via is located at a position that is offset from a first axis on which the first signal connection terminal and the first ground connection terminal are disposed.