专利检索 cpc:"H01L2924/301" 第 1 页

1.

发明申请
PAD STRUCTURE AND INTEGRATED CIRCUIT DIE USING THE SAME 审中-公开

公开(公告)号：US20180261561A1

公开(公告)日：2018-09-13

申请号：US15892460

申请日：2018-02-09

申请人： MEDIATEK INC.

发明人： Chun-Liang CHEN

IPC分类号： H01L23/00

CPC分类号： H01L24/05 , H01L23/562 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05076 , H01L2224/05085 , H01L2224/05093 , H01L2224/05099 , H01L2224/05147 , H01L2224/05551 , H01L2224/05553 , H01L2224/0557 , H01L2224/05573 , H01L2224/05624 , H01L2224/48091 , H01L2224/48106 , H01L2224/48227 , H01L2924/00014 , H01L2924/10253 , H01L2924/14 , H01L2924/301 , H01L2924/3512 , H01L2224/45099

摘要： A pad structure is formed on an IC die and includes a first conductive layer, a dielectric layer, a second conductive layer and a passivation layer. The first conductive layer is formed on an upper surface of the IC die and having a hollow portion. The dielectric layer covers the first conductive layer. The second conductive layer is formed on the dielectric layer and electrically connected to the first conductive layer. The passivation layer covers the second conductive layer and has an opening exposing the second conductive layer for receiving a bonding wire.

2.

发明申请
NON-VOLATILE DUAL IN-LINE MEMORY MODULE (NVDIMM) MULTICHIP PACKAGE 审中-公开

公开(公告)号：US20170338213A1

公开(公告)日：2017-11-23

申请号：US15600690

申请日：2017-05-19

申请人： Sanmina Corporation

发明人： Arvindhkumar Lalam , Alec C. Shen

IPC分类号： H01L25/18 , H01L23/31 , H01L23/00

CPC分类号： H01L25/18 , H01L23/3107 , H01L23/3677 , H01L23/49811 , H01L23/5384 , H01L24/17 , H01L24/49 , H01L25/0655 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73265 , H01L2924/1436 , H01L2924/1438 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/301 , H01L2924/00012 , H01L2924/00

摘要： A single multichip package is provided, comprising: a substrate having opposing upper and lower surfaces. A first die is mounted on the upper surface of the substrate and includes one or more non-volatile memory devices. A second die is mounted on the upper surface of the substrate, and includes at least one of: (a) a non-volatile memory controller that facilitates transfer of data to/from the one or more non-volatile memory devices, (b) a register clock driver for volatile memory devices, and/or (c) one or more multiplexer switches configured to switch between two or more of the volatile memory devices. A plurality of wire bonds connect the first and second dies. A plurality of solder balls are located on the lower surface of the substrate for mounting the single multichip package to a printed circuit board, the plurality of solder balls electrically coupled to the first die and the second die.

3.

发明授权
Integrated circuit package fabrication with die attach paddle having middle channels 有权

公开(公告)号：US09620388B2

公开(公告)日：2017-04-11

申请号：US14941865

申请日：2015-11-16

申请人： Texas Instruments Incorporated

发明人： You Chye How , Maria Christina Bernardo Violante

IPC分类号： H01L21/00 , H01L21/48 , H01L25/00 , H01L25/18 , H01L21/56 , H01L23/00 , H01L23/495 , H01L21/683 , H01L25/065

CPC分类号： H01L21/4821 , H01L21/4828 , H01L21/565 , H01L21/6836 , H01L23/00 , H01L23/49503 , H01L23/49513 , H01L23/49548 , H01L23/49575 , H01L24/27 , H01L24/29 , H01L24/32 , H01L24/48 , H01L24/83 , H01L24/85 , H01L24/94 , H01L25/0655 , H01L25/18 , H01L25/50 , H01L2221/68377 , H01L2224/27003 , H01L2224/27436 , H01L2224/29011 , H01L2224/2919 , H01L2224/2929 , H01L2224/293 , H01L2224/32013 , H01L2224/32245 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/73265 , H01L2224/83191 , H01L2224/83385 , H01L2224/8385 , H01L2224/83851 , H01L2224/94 , H01L2924/00014 , H01L2924/1515 , H01L2924/181 , H01L2924/301 , H01L2924/0665 , H01L2224/45099 , H01L2224/27 , H01L2924/00 , H01L2924/0781

摘要： A method of making an integrated circuit package. A leadframe having a die attach paddle surrounded by lead portions is formed. Middle channels underlying in said die attach paddle portion in a region thereof adapted to receive a first die are formed.

4.

发明申请
Bump Structure and Method of Forming Same 审中-公开
标题翻译：凸块结构及其形成方法

公开(公告)号：US20150357301A1

公开(公告)日：2015-12-10

申请号：US14828147

申请日：2015-08-17

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Guan-Yu Chen , Yu-Wei Lin , Yu-Jen Tseng , Tin-Hao Kuo , Chen-Shien Chen

IPC分类号： H01L23/00

CPC分类号： H01L24/02 , H01L21/4853 , H01L21/76885 , H01L23/49811 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/14 , H01L24/16 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/02125 , H01L2224/02141 , H01L2224/02145 , H01L2224/0215 , H01L2224/0401 , H01L2224/05114 , H01L2224/05124 , H01L2224/05147 , H01L2224/05155 , H01L2224/05647 , H01L2224/10125 , H01L2224/11013 , H01L2224/11019 , H01L2224/1112 , H01L2224/11462 , H01L2224/11472 , H01L2224/13012 , H01L2224/13015 , H01L2224/13017 , H01L2224/13023 , H01L2224/13026 , H01L2224/1308 , H01L2224/13082 , H01L2224/13083 , H01L2224/13111 , H01L2224/13116 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/13166 , H01L2224/13551 , H01L2224/13564 , H01L2224/13565 , H01L2224/1357 , H01L2224/13582 , H01L2224/136 , H01L2224/13686 , H01L2224/1369 , H01L2224/14051 , H01L2224/16148 , H01L2224/16227 , H01L2224/16238 , H01L2224/16503 , H01L2224/81007 , H01L2224/81143 , H01L2224/81191 , H01L2224/81203 , H01L2224/81424 , H01L2224/81439 , H01L2224/81444 , H01L2224/81447 , H01L2224/8181 , H01L2224/81895 , H01L2224/8192 , H01L2224/81948 , H01L2225/06513 , H01L2924/04941 , H01L2924/07025 , H01L2924/181 , H01L2924/301 , H01L2924/35 , Y10T29/49144 , H01L2924/00014 , H01L2924/014 , H01L2924/05432 , H01L2924/053 , H01L2924/00 , H01L2924/00012

摘要： An embodiment bump on trace (BOT) structure includes a contact element supported by an integrated circuit, an under bump metallurgy (UBM) feature electrically coupled to the contact element, a metal bump on the under bump metallurgy feature, and a substrate trace on a substrate, the substrate trace coupled to the metal bump through a solder joint and intermetallic compounds, a ratio of a first cross sectional area of the intermetallic compounds to a second cross sectional area of the solder joint greater than forty percent.

摘要翻译： 轨迹（BOT）结构上的实施例凸块包括由集成电路支撑的接触元件，电耦合到接触元件的凸块下金属（UBM）特征，凸起下金属冶金特征上的金属凸块，以及衬底迹线衬底，通过焊接接头和金属间化合物耦合到金属凸块的衬底迹线，金属间化合物的第一横截面积与焊料接头的第二横截面积的比率大于百分之四十。

5.

发明授权
Lead-free solder bump bonding structure 有权
标题翻译：无铅焊料接合结构

公开(公告)号：US08847390B2

公开(公告)日：2014-09-30

申请号：US13951596

申请日：2013-07-26

申请人： Eiji Hashino , Shinji Ishikawa , Shinichi Terashima , Masamoto Tanaka

发明人： Eiji Hashino , Shinji Ishikawa , Shinichi Terashima , Masamoto Tanaka

IPC分类号： H01L23/48 , H01L23/52 , H01L29/40 , H01L23/498

CPC分类号： H01L23/49866 , B23K35/0244 , B23K35/025 , B23K35/262 , B23K2101/36 , B23K2101/40 , B23K2101/42 , H01L23/49811 , H01L23/49816 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/16 , H01L24/81 , H01L2224/0381 , H01L2224/03828 , H01L2224/0401 , H01L2224/05647 , H01L2224/05655 , H01L2224/1132 , H01L2224/11334 , H01L2224/1134 , H01L2224/11848 , H01L2224/11849 , H01L2224/119 , H01L2224/13111 , H01L2224/16225 , H01L2224/16227 , H01L2224/16503 , H01L2224/81024 , H01L2224/81048 , H01L2224/81191 , H01L2224/81447 , H01L2224/81815 , H01L2224/81948 , H01L2924/301 , H01L2924/381 , H05K3/3436 , H05K3/3463 , H05K2201/0769 , H05K2203/041 , H01L2924/01028 , H01L2924/01029 , H01L2924/01047 , H01L2924/01027 , H01L2924/01026 , H01L2924/01015 , H01L2924/01012 , H01L2924/01032 , H01L2924/01046 , H01L2924/01025 , H01L2924/01013 , H01L2924/01051 , H01L2924/01049 , H01L2924/0103 , H01L2924/00014 , H01L2924/00012 , H01L2924/00015

摘要： According to a lead-free solder bump bonding structure, by causing the interface (IMC interface) of the intermetallic compound layer at a lead-free-solder-bump side to have scallop shapes of equal to or less than 0.02 [portions/μm] without forming in advance an Ni layer as a barrier layer on the surfaces of respective Cu electrodes of first and second electronic components like conventional technologies, a Cu diffusion can be inhibited, thereby inhibiting an occurrence of an electromigration. Hence, the burden at the time of manufacturing can be reduced by what corresponds to an omission of the formation process of the Ni layer as a barrier layer on the Cu electrode surfaces, and thus a lead-free solder bump bonding structure can be provided which reduces a burden at the time of manufacturing in comparison with conventional technologies and which can inhibit an occurrence of an electromigration.

摘要翻译： 根据无铅焊料接合结构，通过使无铅焊料凸点侧的金属间化合物层的界面（IMC界面）具有等于或小于0.02 [份/μm]的扇形，在不像传统技术那样在第一和第二电子部件的各个Cu电极的表面上预先形成Ni层作为阻挡层的情况下，可以抑制Cu扩散，从而抑制电迁移的发生。因此，可以通过对作为Cu电极表面上的阻挡层的Ni层的形成处理的省略来减少制造时的负担，从而可以提供无铅焊料凸块接合结构，其中，与传统技术相比，减少制造时的负担，并且可以抑制电迁移的发生。

6.

发明申请
BUMPING PROCESS AND STRUCTURE THEREOF 有权
标题翻译：保鲜工艺及其结构

公开(公告)号：US20130213702A1

公开(公告)日：2013-08-22

申请号：US13852663

申请日：2013-03-28

申请人： Chipbond Technology Corporation

发明人： Chin-Tang Hsieh , Chih-Ming Kuo

IPC分类号： H05K1/11

CPC分类号： H05K1/111 , H01L21/4846 , H01L23/3192 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05147 , H01L2224/05541 , H01L2224/05547 , H01L2224/05556 , H01L2224/05557 , H01L2224/05565 , H01L2224/05567 , H01L2224/05578 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05687 , H01L2224/1147 , H01L2224/11912 , H01L2224/13005 , H01L2224/13006 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/13565 , H01L2224/13687 , H01L2924/00014 , H01L2924/301 , H01L2924/384 , Y10T428/12396 , H01L2924/00012 , H01L2924/05042 , H01L2924/05442 , H01L2924/058 , H01L2224/05552

摘要： A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon.

摘要翻译： 凸起工艺包括在基底上形成具有铜的金属层的步骤，并且具有铜的金属层包括多个第一区域和第二区域; 用铜在金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口; 在所述开口内形成多个铜凸块，每个所述铜凸块覆盖所述第一区域并且包括第一顶表面; 在所述第一顶表面上形成连接层; 去除光致抗蚀剂层; 去除所述第二区域并且使得所述第一区域中的每一个形成凸起下冶金层，其中所述凸起下的冶金层，所述铜凸块和所述连接层具有其对应的周壁，以及覆盖在第一区上形成的第一保护层的覆盖部分连接层可以覆盖那些外围壁以防止电离现象。

7.

发明授权
Bumping process and structure thereof 有权
标题翻译：冲击过程及其结构

公开(公告)号：US08450203B2

公开(公告)日：2013-05-28

申请号：US13187353

申请日：2011-07-20

申请人： Chin-Tang Hsieh , Chih-Ming Kuo

发明人： Chin-Tang Hsieh , Chih-Ming Kuo

IPC分类号： H01L21/44

CPC分类号： H05K1/111 , H01L21/4846 , H01L23/3192 , H01L23/49811 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0347 , H01L2224/03912 , H01L2224/03914 , H01L2224/0401 , H01L2224/05147 , H01L2224/05541 , H01L2224/05547 , H01L2224/05556 , H01L2224/05557 , H01L2224/05565 , H01L2224/05567 , H01L2224/05578 , H01L2224/05583 , H01L2224/05647 , H01L2224/05655 , H01L2224/05687 , H01L2224/1147 , H01L2224/11912 , H01L2224/13005 , H01L2224/13006 , H01L2224/13017 , H01L2224/13018 , H01L2224/13022 , H01L2224/13083 , H01L2224/13147 , H01L2224/13155 , H01L2224/13565 , H01L2224/13687 , H01L2924/00014 , H01L2924/301 , H01L2924/384 , Y10T428/12396 , H01L2924/00012 , H01L2924/05042 , H01L2924/05442 , H01L2924/058 , H01L2224/05552

摘要： A bumping process comprises steps of forming a metal layer with copper on a substrate, and the metal layer with copper comprises a plurality of first zones and second zones; forming a photoresist layer on the metal layer with copper; patterning the photoresist layer to form a plurality of openings; forming a plurality of copper bumps within the openings, each of the copper bumps covers the first zones and comprises a first top surface; forming a connection layer on the first top surface; removing the photoresist layer; removing the second zones and enabling each of the first zones to form an under bump metallurgy layer, wherein the under bump metallurgy layer, the copper bump, and the connection layer possess their corresponded peripheral walls, and covering sections of a first protective layer formed on the connection layer may cover those peripheral walls to prevent ionization phenomenon.

摘要翻译： 凸起工艺包括在基底上形成具有铜的金属层的步骤，并且具有铜的金属层包括多个第一区域和第二区域; 用铜在金属层上形成光致抗蚀剂层; 图案化光致抗蚀剂层以形成多个开口; 在所述开口内形成多个铜凸块，每个所述铜凸块覆盖所述第一区域并且包括第一顶表面; 在所述第一顶表面上形成连接层; 去除光致抗蚀剂层; 去除所述第二区域并且使得所述第一区域中的每一个形成凸起下冶金层，其中所述凸起下的冶金层，所述铜凸块和所述连接层具有其对应的周壁，以及覆盖在第一区上形成的第一保护层的覆盖部分连接层可以覆盖那些外围壁以防止电离现象。

8.

发明授权
Molded semiconductor package with high voltage isolation 有权

公开(公告)号：US11817407B2

公开(公告)日：2023-11-14

申请号：US17746306

申请日：2022-05-17

申请人： Infineon Technologies AG

发明人： Shao Ping Wan , Eric Brion Acquitan , Dexter Reynoso , Jürgen Schredl , Woon Yik Yong

IPC分类号： H01L23/00 , H01L23/31 , H01L21/56

CPC分类号： H01L24/05 , H01L21/565 , H01L23/3142 , H01L24/45 , H01L24/85 , H01L2224/0569 , H01L2924/301

摘要： A molded semiconductor package includes: a semiconductor die attached to a substrate, the semiconductor die having a bond pad at a first side of the semiconductor die which faces away from the substrate and an insulating layer covering the first side; an electrical conductor attached to a part of the bond pad exposed by an opening in the insulating layer; a mold compound encasing the semiconductor die; and an electrically insulative material filling the opening in the insulating layer and sealing the part of the bond pad exposed by the opening in the insulating layer. The electrically insulative material separates the mold compound from the part of the bond pad exposed by the opening in the insulating layer. A corresponding method of producing the molded semiconductor package also is described.