公开(公告)号：US10360121B2

公开(公告)日：2019-07-23

申请号：US14734658

申请日：2015-06-09

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih ,  Wei-Ying Lu

IPC: G06F11/00 ,  G06F11/26 ,  G06F11/07 ,  G06F11/22 ,  G06F11/36 ,  G06F11/32

Abstract: Embodiments generally relate to a universal debug design which involves integrating a debug controller and a debug card with display together into a single debug design. Debug codes, such as power-on self-test (POST) codes and other error codes, are generated by various subsystems of a server-related system. The codes are transmitted to a controller, which stores the codes in memory. In some embodiments, a multiplexer outputs one debug code from the multitude of received codes, based on a user or event selecting which desired debug code should be displayed. In some embodiments, a decoder converts and sends the LED display signals to a debug card, which displays the debug code on a 7-segment LED display.

公开(公告)号：US20160127167A1

公开(公告)日：2016-05-05

申请号：US14593774

申请日：2015-01-09

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih ,  Wei-Ying Lu

IPC: H04L12/24

CPC classification number: H04L41/0226

Abstract: In some implementations, service controllers of a computing device are associated with various disparate components of the computing device, and in response to a command issued to any one of the components, the service controllers may communicate with each other in order to transmit data responsive to the command. For example, a computing device may comprise a Baseboard Management Controller (BMC) and a Serial Attached SCSI Expander card (SAS Expander). The BMC of computing device receives a remote command requesting status of a hard drive coupled to the computing device, and the BMC communicates the command to the SAS Expander, for example over a system bus of the computing device. The SAS Expander retrieves a response to the command and communicates the response to the BMC, which then transmits the response to the remote site.

Abstract translation: 在一些实现中，计算设备的服务控制器与计算设备的各种不同的组件相关联，并且响应于发布给组件中的任何一个的命令，服务控制器可以彼此通信，以便响应于 命令。 例如，计算设备可以包括基板管理控制器（BMC）和串行连接的SCSI扩展器卡（SAS Expander）。 计算设备的BMC接收请求与计算设备耦合的硬盘驱动器的状态的远程命令，并且BMC例如通过计算设备的系统总线将命令传达到SAS扩展器。 SAS扩展器检索对该命令的响应，并将响应传达给BMC，BMC将响应发送到远程站点。

公开(公告)号：US12174758B2

公开(公告)日：2024-12-24

申请号：US18156251

申请日：2023-01-18

Applicant: Quanta Computer Inc.

Inventor： Han-Chuan Tsai ,  Wei-Hung Lin ,  Yen-Ping Tung ,  Sz-Chin Shih

IPC: G06F13/16

Abstract: A system and method for a configurable computer system architecture is disclosed. The computer system architecture includes a power distribution board including a configuration identification strapping. The architecture includes a first node having a first processor and a first baseboard management controller (BMC) coupled to the power distribution board via an internal communication channel. A second node, identical to the first node, has a second processor and a second BMC coupled to the power distribution board via the internal communication channel. The configuration identification strapping is one of a first configuration readable by the first and second BMCs with two nodes operating as independent devices, or a second configuration readable by the first and second BMCs with two nodes operating as a single device. The first BMC serves as a master BMC and the second BMC serves as a slave BMC in the second configuration.

公开(公告)号：US10333771B2

公开(公告)日：2019-06-25

申请号：US14883161

申请日：2015-10-14

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih

IPC: H04L12/24

Abstract: A device, such as a baseboard management controller, monitors a physical-layer device in a server and at least one network connector/cable connected to the physical-layer device, determines a status of the physical-layer device or a status of the at least one network connector/cable indicates at least one of a warning or a failure, and transmits an alert corresponding to the at least one of the warning or the failure to a rack management controller.

公开(公告)号：USRE46520E1

公开(公告)日：2017-08-22

申请号：US14686458

申请日：2015-04-14

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih

IPC: G06F1/00 ,  G06F11/00 ,  H04L12/24 ,  H04L12/26 ,  H04L12/56 ,  G06F1/32 ,  G06F11/30 ,  H04L12/12 ,  G06F11/07 ,  H04L12/931

CPC classification number: G06F11/00 ,  G06F1/3209 ,  G06F1/3287 ,  G06F11/0709 ,  G06F11/0793 ,  G06F11/3006 ,  G06F11/3055 ,  H04L12/12 ,  H04L41/00 ,  H04L43/00 ,  H04L49/356 ,  Y02D10/171 ,  Y02D50/40

Abstract: A server cluster including a network switch and multiple server nodes is provided. The network switch is connected to an external network. Each server node performs an operation system and respectively includes a network port, a network chip and a south bridge chip. The network port is connected to the network switch via a cable. The network chip outputs a power-off signal according to a received power-off packet after the network switch is started. The south bridge chip outputs a shutdown signal to shut down the server node according to the power-off signal when the server node is turned on and the operation system is working normally.

公开(公告)号：US10929320B1

公开(公告)日：2021-02-23

申请号：US16706330

申请日：2019-12-06

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih ,  Shuen-Hung Wang ,  Jui-Chi Huang

IPC: G06F13/20

Abstract: A system and method for generating a control bifurcation signal in accordance with the Open Compute Project (OCP) Specification. An OCP device is provided that has a bifurcation function with an input to activate a bus bifurcation function. An input/output control circuit having an output coupled to a bifurcation control line coupled to the OCP device is provided. The input/output control circuit is operable to provide a bifurcation control signal to the OCP device over the bifurcation control line during an auxiliary power phase transition period of powering-on the OCP device.

公开(公告)号：US10101764B2

公开(公告)日：2018-10-16

申请号：US14953975

申请日：2015-11-30

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih

IPC: G06F13/38 ,  G06F13/40 ,  G06F13/42 ,  G06F1/12

Abstract: A method for automatic clock configurations is performed by a system having a host and a peripheral device. The host indicates on a first general-purpose input/output (GPIO) of a peripheral interface connecting the host and the peripheral device, whether the host supports a first clock configuration. The peripheral device receives from the first GPIO whether the host supports the first clock configuration. The peripheral device selects, in response to the host supporting the first clock configuration, use of a local clock of the peripheral device. The peripheral device selects, in response to the host not supporting the first clock configuration, use of a common clock of the host.

公开(公告)号：US09794120B2

公开(公告)日：2017-10-17

申请号：US14686217

申请日：2015-04-14

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih

IPC: H04L12/24 ,  G06F13/38 ,  G06F13/12

CPC classification number: H04L41/0816 ,  G06F13/128 ,  G06F13/385 ,  H04L41/20

Abstract: A controller in a server system can determine whether to share a network connection of the server system. In response to determining to share the network connection, the controller can disable a dedicated network connection between the controller and a network interface controller (NIC) in the server system, enable a first shared network connection between the controller and a computing module in the server system, and enable a second shared network connection between the computing module and the NIC. In response to determining not to share the network connection, the controller can enable the dedicated network connection between the controller and the NIC.

公开(公告)号：US11693814B2

公开(公告)日：2023-07-04

申请号：US17127279

申请日：2020-12-18

Applicant: QUANTA COMPUTER INC.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4282 ,  G06F13/409 ,  G06F13/4022 ,  G06F13/4068 ,  G06F13/4221

Abstract: A system and device for expanding accessible memory of a processor is provided. An interposer is coupled to the processor and a memory module. The interposer is coupled to a first connection and a second connection. The interposer includes a memory controller circuit. The memory controller circuit receives signals from the processor, using the first connection, and transmits the received signals to the memory module, using the second connection. The interposer expands memory access without an unnecessary second processor.

公开(公告)号：US11269803B1

公开(公告)日：2022-03-08

申请号：US17108733

申请日：2020-12-01

Applicant: Quanta Computer Inc.

Inventor： Le-Sheng Chou ,  Sz-Chin Shih ,  Shuen-Hung Wang

IPC: G06F13/36 ,  G06F13/42 ,  G06F13/40

Abstract: A system and method for providing efficient communication between a processor and a device. An interposer is provided to send signals from the processor to the device. The interposer includes a printed circuit board, a first interconnection port communicating with the processor, and a second interconnection port communicating with the device. A retimer/redriver circuit is coupled to the first interconnection port and the second interconnection port, and the retimer/redriver circuit routes signals from the first interconnection port to the second interconnection port.