公开(公告)号：US5668411A

公开(公告)日：1997-09-16

申请号：US685159

申请日：1996-07-23

申请人： Qi-Zhong Hong ,  Shin-Puu Jeng ,  Robert H. Havemann

发明人： Qi-Zhong Hong ,  Shin-Puu Jeng ,  Robert H. Havemann

IPC分类号： H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L29/78 ,  H01L21/44 ,  H01L29/43

CPC分类号： H01L21/76876 ,  H01L21/76841 ,  H01L23/5226 ,  H01L23/53223 ,  H01L2221/1078 ,  H01L2924/0002 ,  Y10S257/915

摘要： A diffusion barrier trilayer 42 is comprised of a bottom layer 44, a seed layer 46 and a top layer 48. The diffusion barrier trilayer 42 prevents reaction of metallization layer 26 with the top layer 48 upon heat treatment, resulting in improved sheet resistance and device speed.

摘要翻译： 扩散阻挡三层42由底层44，种子层46和顶层48组成。扩散阻挡三层42防止金属化层26与顶层48在热处理时的反应，导致改善的薄层电阻和装置 速度。

公开(公告)号：US5892282A

公开(公告)日：1999-04-06

申请号：US757776

申请日：1996-11-27

申请人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Shin-puu Jeng

发明人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Shin-puu Jeng

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

摘要： Methods are provided for the construction of metal-to-metal connections between non-adjacent layers in a structure, such as a semiconductor device. A first metal conductor layer is provided along a substrate. An anti-reflection cap is provided in overlying relation with said first conductor layer. At least a portion of the dielectric layer and the anti-reflection cap is removed to define a passage which extends from an upper surface of the dielectric layer to the first metal conductor. The passage is substantially filled with a fill metal, and a second metal conductor layer is applied over at least a portion of the dielectric layer and the substantially filled passage to electrically connect the first and second metal conductors. A diffusion liner can optionally be applied to the passage prior to application of the fill metal. The passage fill metal and second conductor layer can be integrally formed, and the fill metal and at least one of the conductor layers are formed from the same matrix metal.

摘要翻译： 提供了用于在诸如半导体器件的结构中的非相邻层之间的金属 - 金属连接的构造的方法。 沿着基板设置第一金属导体层。 防反射盖以与所述第一导体层重叠的关系提供。 去除介电层和防反射盖的至少一部分以限定从电介质层的上表面延伸到第一金属导体的通道。 通道基本上填充有填充金属，并且第二金属导体层被施加在电介质层和基本上填充的通道的至少一部分上以电连接第一和第二金属导体。 在施加填充金属之前，扩散衬垫可以可选地施加到通道。 通道填充金属和第二导体层可以一体地形成，并且填充金属和至少一个导体层由相同的基体金属形成。

公开(公告)号：US6008117A

公开(公告)日：1999-12-28

申请号：US820927

申请日：1997-03-19

申请人： Qi-Zhong Hong ,  Shin-Puu Jeng ,  Wei-Yung Hsu

发明人： Qi-Zhong Hong ,  Shin-Puu Jeng ,  Wei-Yung Hsu

IPC分类号： H01L21/768 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834

摘要： A method is provided for forming sidewall diffusion barriers from a dielectric material. A trench or via is formed in a semiconductor device. A layer of dielectric material is deposited over the surfaces of the semiconductor device. The deposited layer of dielectric material is removed from all surfaces except the sidewall of the trench or via, thereby forming the dielectric diffusion barriers on the sidewall. Because dielectric materials have an amorphous structure which does not readily permit diffusion, impurities do not need to be added to the dielectric diffusion barriers. Furthermore, dielectric diffusion barriers produce a smaller RC time delay relative to metallic diffusion barriers having a comparable thickness.

摘要翻译： 提供了用于从电介质材料形成侧壁扩散阻挡层的方法。 在半导体器件中形成沟槽或通孔。 介电材料层沉积在半导体器件的表面上。 介电材料的沉积层除了沟槽或通孔的侧壁以外的所有表面被去除，从而在侧壁上形成电介质扩散阻挡层。 由于介电材料具有不容易扩散的非晶结构，所以不需要将杂质添加到电介质扩散阻挡层中。 此外，相对于具有相当厚度的金属扩散阻挡层，电介质扩散屏障产生较小的RC时间延迟。

公开(公告)号：US5985763A

公开(公告)日：1999-11-16

申请号：US970961

申请日：1997-11-14

申请人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Shin-puu Jeng

发明人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Shin-puu Jeng

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/441

CPC分类号： H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53219 ,  H01L23/53223 ,  H01L2924/0002 ,  Y10S257/915

摘要： Methods are provided for the construction of metal-to-metal connections between non-adjacent layers in a structure, such as a semiconductor device. A first metal conductor layer is provided along a substrate. An anti-reflection cap is provided in overlying relation with said first conductor layer. At least a portion of the dielectric layer and the anti-reflection cap is removed to define a passage which extends from an upper surface of the dielectric layer to the first metal conductor. The passage is substantially filled with a fill metal, and a second metal conductor layer is applied over at least a portion of the dielectric layer and the substantially filled passage to electrically connect the first and second metal conductors. A diffusion liner can optionally be applied to the passage prior to application of the fill metal. The passage fill metal and second conductor layer can be integrally formed, and the fill metal and at least one of the conductor layers are formed from the same matrix metal.

摘要翻译： 提供了用于在诸如半导体器件的结构中的非相邻层之间的金属 - 金属连接的构造的方法。 沿着基板设置第一金属导体层。 防反射盖以与所述第一导体层重叠的关系提供。 去除介电层和防反射盖的至少一部分以限定从电介质层的上表面延伸到第一金属导体的通道。 通道基本上填充有填充金属，并且第二金属导体层被施加在电介质层和基本上填充的通道的至少一部分上以电连接第一和第二金属导体。 在施加填充金属之前，扩散衬垫可以可选地施加到通道。 通道填充金属和第二导体层可以一体地形成，并且填充金属和至少一个导体层由相同的基体金属形成。

公开(公告)号：US06355559B1

公开(公告)日：2002-03-12

申请号：US09706275

申请日：2000-11-03

申请人： Robert H. Havemann ,  Qi-Zhong Hong ,  Girish Dixit

发明人： Robert H. Havemann ,  Qi-Zhong Hong ,  Girish Dixit

IPC分类号： H01L214763

CPC分类号： H01L21/76849 ,  H01L21/76852 ,  H01L21/76856 ,  H01L21/76858 ,  H01L21/76886

摘要： A method for forming a metal interconnect having a self-aligned transition metal-nitride barrier (124). After the metal interconnect lines (118) are formed, a transition metal (120) is deposited over the surface of the metal interconnect lines (118) and reacted in to form a metal-compound (122). The metal-compound (122) is then annealed in a nitrogen ambient to form a barrier layer (114) at the surface of the metal interconnect lines (118).

摘要翻译： 一种用于形成具有自对准过渡金属氮化物屏障（124）的金属互连的方法。 在金属互连线（118）形成之后，过渡金属（120）沉积在金属互连线（118）的表面上并反应以形成金属化合物（122）。 金属化合物（122）然后在氮气环境中退火以在金属互连线（118）的表面形成阻挡层（114）。

公开(公告)号：US06358849B1

公开(公告)日：2002-03-19

申请号：US09467680

申请日：1999-12-21

申请人： Robert H. Havemann ,  Girish A. Dixit ,  Manoj Jain ,  Eden Zielinski ,  Qi-Zhong Hong ,  Jeffrey West

发明人： Robert H. Havemann ,  Girish A. Dixit ,  Manoj Jain ,  Eden Zielinski ,  Qi-Zhong Hong ,  Jeffrey West

IPC分类号： H01L21302

CPC分类号： H01L21/76808 ,  H01L21/31053 ,  H01L21/76224 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867

摘要： A dual inlaid interconnect fabrication method using a temporary filler in a via during trench etch and removal of the filler after trench etch. This provides via bottom protection during trench etch.

摘要翻译： 一种双嵌入互连制造方法，在沟槽蚀刻中沟槽蚀刻和去除填充物之后，在通孔中使用临时填料。 这在沟槽蚀刻期间通过底部保护提供。

公开(公告)号：US6077782A

公开(公告)日：2000-06-20

申请号：US23424

申请日：1998-02-13

申请人： Wei-Yung Hsu ,  Qi-Zhong Hong ,  Robert H. Havemann

发明人： Wei-Yung Hsu ,  Qi-Zhong Hong ,  Robert H. Havemann

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/44

CPC分类号： H01L21/76814 ,  H01L21/76843 ,  H01L21/76862 ,  H01L21/76882 ,  H01L23/53223 ,  H01L2924/0002

摘要： A method to improve the texture of titanium and aluminum to reduce electromigration by controlling the deposition conditions and the texture of the substrates. Aluminum films can develop strong texture, when titanium is used underneath aluminum. However, to prevent the interaction between aluminum and titanium, a layer of TiN or other barrier is necessary. Fortunately, TiN has a similar atom arrangement on the plane as that of aluminum and titanium . Therefore, by controlling the orientation of titanium using a pre-sputter argon etch and low titanium deposition temperature, the texture of titanium can be transferred to TiN, and subsequently to aluminum.

摘要翻译： 通过控制沉积条件和基板的质地，改善钛和铝的织构以减少电迁移的方法。 当铝在铝下使用时，铝膜可以发展出强烈的<111>质感。 然而，为了防止铝和钛之间的相互作用，需要一层TiN或其它屏障。 幸运的是，TiN在<111>平面上具有与铝<111>和钛<002>相似的原子排列。 因此，通过使用预溅射氩蚀刻和低钛沉积温度控制钛的取向，钛的织构可以转移到TiN，然后转移到铝。

公开(公告)号：US06245672B1

公开(公告)日：2001-06-12

申请号：US09177412

申请日：1998-10-23

申请人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Jiong-Ping Lu ,  Robert H. Havemann

发明人： Qi-Zhong Hong ,  Wei-Yung Hsu ,  Jiong-Ping Lu ,  Robert H. Havemann

IPC分类号： H01L214763

CPC分类号： H01L21/76856 ,  H01L21/76843 ,  H01L21/76855

摘要： An integrated circuit structure including copper metallization (20, 32, 42), and a method of fabricating the same are disclosed. The structure includes a doped region (7) of a silicon substrate (9), which is typically clad with a metal silicide film (12) formed by way of direct react silicidation. At contact locations (CT) at which the copper metallization (20, 32, 42) is to make contact to the doped region (7), a chemically-densified barrier layer (16, 30, 38) provides a diffusion barrier to the overlying copper metallization (20, 32, 42). The chemically-densified barrier layer (16, 30, 38) is formed by an anneal of the structure to react impurities (14, 28, 36) with the underlying refractory-metal-based film (12, 34); the impurities are introduced by way of wet chemistry, plasma bombardment, or from the ambient in which the structure is annealed.

摘要翻译： 公开了一种包括铜金属化（20,32,42）的集成电路结构及其制造方法。 该结构包括硅衬底（9）的掺杂区域（7），其通常用通过直接反应硅化形成的金属硅化物膜（12）包覆。 在铜金属化层（20,32,42）将与掺杂区域（7）接触的接触位置（CT）处，化学致密化的势垒层（16,30,38）为覆盖层 铜金属化（20,32,42）。 化学致密化的阻挡层（16,30,38）通过该结构的退火形成，以使杂质（14,28,36）与下面的耐熔金属基膜（12,34）反应; 杂质通过湿化学，等离子体轰击或结构退火的环境引入。

公开(公告)号：US5605724A

公开(公告)日：1997-02-25

申请号：US407353

申请日：1995-03-20

申请人： Qi-Zhong Hong ,  Robert H. Havemann

发明人： Qi-Zhong Hong ,  Robert H. Havemann

IPC分类号： C23C14/06 ,  C23C14/34 ,  C23C16/50 ,  H01L21/203 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H05H1/00

CPC分类号： H01L21/76856 ,  H01L21/76843

摘要： A method for minimizing reaction between metal conductors and other metals to minimize change in sheet resistance of the conductors upon heat treatment which includes providing a substrate. The substrate is preferably one of a dielectric, a metal or a semiconductor. A metallic diffusion barrier layer, preferably one of TiN, TiW or TiWN and preferably having a thickness of from about 10 nanometers to about 100 nanometers, is deposited on the substrate, preferably by one of sputtering, electron beam evaporation or chemical vapor deposition. The exposed surface of the metallic diffusion barrier layer is treated with a plasma, preferably an oxygen plasma, a nitrous oxide plasma or a plasma of an oxygen-containing species. An electrical conductor, preferably one of aluminum, aluminum-metal alloys, copper or copper-metal alloys and preferably having a thickness of from about 100 nanometers to about 1200 nanometers, is then deposited on the plasma-treated surface of the metallic diffusion barrier layer. The layers can be formed as one of a blanket or continuous films over the substrate. The conductor can then be patterned.

摘要翻译： 一种用于使金属导体和其它金属之间的反应最小化的方法，以使热处理时导体的薄层电阻变化最小化，包括提供基板。 基板优选为电介质，金属或半导体中的一种。 优选通过溅射，电子束蒸发或化学气相沉积中的一种沉积在金属扩散阻挡层上，优选TiN，TiW或TiWN中的一种，优选具有约10纳米至约100纳米的厚度。 金属扩散阻挡层的暴露表面用等离子体，优选氧等离子体，一氧化二氮等离子体或含氧物质的等离子体进行处理。 然后将电导体（优选铝，铝 - 金属合金，铜或铜 - 金属合金中的一种）优选地具有约100纳米至约1200纳米的厚度，然后沉积在金属扩散阻挡层的等离子体处理的表面上 。 这些层可以形成为衬底上的覆盖层或连续膜之一。 然后可以对导体进行图案化。

公开(公告)号：US07192863B2

公开(公告)日：2007-03-20

申请号：US10903711

申请日：2004-07-30

申请人： Lu Zhijian ,  Qi-Zhong Hong

发明人： Lu Zhijian ,  Qi-Zhong Hong

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808

摘要： A dual damascene process employs a via fill material (38) with an etch rate that is within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which a trench (48) and via (50) are being formed. In one embodiment, an organic via fill material plug (40) is employed in conjunction with a bottom anti-reflective coating (BARC) material layer (42). Both the organic via fill material plug (40) and the BARC material layer (42) are selected to have a material with an etch rate that within 60% of an etch rate that an underlying dielectric layer (34) etches for a given dielectric etch chemistry in which the trench (48) and via (50) are formed.

摘要翻译： 双镶嵌工艺采用通孔填充材料（38），蚀刻速率在蚀刻速率的60％以内，下面的介电层（34）蚀刻用于给定电介质蚀刻化学品，其中沟槽（48）和通孔（ 50）正在形成。 在一个实施例中，有机通孔填充材料塞（40）与底部抗反射涂层（BARC）材料层（42）结合使用。 有机通孔填充材料塞（40）和BARC材料层（42）都被选择为具有蚀刻速率在蚀刻速率的60％以内的材料，底层介电层（34）蚀刻用于给定的电介质蚀刻 形成沟槽（48）和通孔（50）的化学。