Variable doping of metal plugs for enhanced reliability
    2.
    发明授权
    Variable doping of metal plugs for enhanced reliability 有权
    金属插头的可变掺杂可提高可靠性

    公开(公告)号:US6130156A

    公开(公告)日:2000-10-10

    申请号:US281538

    申请日:1999-03-30

    摘要: A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via. The first layer of electrically conductive interconnect is preferably aluminum, the first layer of electrically conductive metal is preferably a metal containing from about one percent by weight to about one hundred percent copper and the rest essentially aluminum and the second layer of electrically conductive metal is preferably copper doped aluminum having a lower copper content than the first electrically conductive layer.

    摘要翻译: 一种制造互连的方法,其中最初提供第一层导电互连(3)。 形成通孔(7),其通过延伸到第一互连层的壁限定。 在导电互连和导电金属(11)的第一层之间形成一层钛(9)。 第一层导电金属形成在通孔的壁上,具有相对于特定蚀刻物质的预定蚀刻速率,并且第二层导电金属(13)形成在具有蚀刻的第一导电金属层上 相对于比第一层大的特定蚀刻物质的速率,并且优选地延伸到通孔中。 导电互连的第一层优选为铝,第一层导电金属优选为含有约1%至约100%铜的金属,其余基本上为铝,而第二层导电金属优选为 铜掺杂的铝的铜含量低于第一导电层。

    Low pressure, low temperature, semiconductor gap filling process
    3.
    发明授权
    Low pressure, low temperature, semiconductor gap filling process 失效
    低压,低温,半导体缺口填充工艺

    公开(公告)号:US06333265B1

    公开(公告)日:2001-12-25

    申请号:US08766199

    申请日:1996-12-12

    IPC分类号: H01L2144

    摘要: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;

    摘要翻译: 提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。 这些结构在不超过约300℃,优选在约20°-275℃之间的较低温度下填充,该温度范围允许使用低介电常数(κ)聚合物(即, 〜3.0)。 优选地,空腔设置有不含钛的衬垫以促进空腔填充,并且空腔填充有CVD铝,其通过在大气压至约50MPa的压力下的强力填充物引入空腔中,并且优选地 在约100°-300℃的温度下不超过约30Mpa。以上述方式填充的空腔表现出比通过常规实践填充的结构小至多30%的电阻水平。

    Low pressure, low temperature, semiconductor gap filling process
    5.
    发明授权
    Low pressure, low temperature, semiconductor gap filling process 有权
    低压,低温,半导体缺口填充工艺

    公开(公告)号:US06589865B2

    公开(公告)日:2003-07-08

    申请号:US09899194

    申请日:2001-07-06

    IPC分类号: H01L214763

    摘要: A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;

    摘要翻译: 提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。 这些结构在不超过约300℃,优选在约20°-275℃之间的较低温度下填充,该温度范围允许使用低介电常数(κ)聚合物(即, 〜3.0)。 优选地,空腔设置有元素的无钛衬里以便于空腔填充,并且空腔填充有CVD铝,其通过在大气压至约50MPa的压力下的强力填充物引入空腔中,并且优选地不 大约30MPa,在约100°-300℃的温度范围内。以上述方式填充的凹坑表现出比通过常规实践填充的结构低30%的电阻水平。

    Passivation of inlaid metallization
    6.
    发明授权
    Passivation of inlaid metallization 有权
    嵌入金属化钝化

    公开(公告)号:US06355559B1

    公开(公告)日:2002-03-12

    申请号:US09706275

    申请日:2000-11-03

    IPC分类号: H01L214763

    摘要: A method for forming a metal interconnect having a self-aligned transition metal-nitride barrier (124). After the metal interconnect lines (118) are formed, a transition metal (120) is deposited over the surface of the metal interconnect lines (118) and reacted in to form a metal-compound (122). The metal-compound (122) is then annealed in a nitrogen ambient to form a barrier layer (114) at the surface of the metal interconnect lines (118).

    摘要翻译: 一种用于形成具有自对准过渡金属氮化物屏障(124)的金属互连的方法。 在金属互连线(118)形成之后,过渡金属(120)沉积在金属互连线(118)的表面上并反应以形成金属化合物(122)。 金属化合物(122)然后在氮气环境中退火以在金属互连线(118)的表面形成阻挡层(114)。

    Method of forming diffusion barriers for copper metallization in integrated cirucits
    7.
    发明授权
    Method of forming diffusion barriers for copper metallization in integrated cirucits 有权
    在集成的铁芯中形成铜金属化的扩散阻挡层的方法

    公开(公告)号:US06245672B1

    公开(公告)日:2001-06-12

    申请号:US09177412

    申请日:1998-10-23

    IPC分类号: H01L214763

    摘要: An integrated circuit structure including copper metallization (20, 32, 42), and a method of fabricating the same are disclosed. The structure includes a doped region (7) of a silicon substrate (9), which is typically clad with a metal silicide film (12) formed by way of direct react silicidation. At contact locations (CT) at which the copper metallization (20, 32, 42) is to make contact to the doped region (7), a chemically-densified barrier layer (16, 30, 38) provides a diffusion barrier to the overlying copper metallization (20, 32, 42). The chemically-densified barrier layer (16, 30, 38) is formed by an anneal of the structure to react impurities (14, 28, 36) with the underlying refractory-metal-based film (12, 34); the impurities are introduced by way of wet chemistry, plasma bombardment, or from the ambient in which the structure is annealed.

    摘要翻译: 公开了一种包括铜金属化(20,32,42)的集成电路结构及其制造方法。 该结构包括硅衬底(9)的掺杂区域(7),其通常用通过直接反应硅化形成的金属硅化物膜(12)包覆。 在铜金属化层(20,32,42)将与掺杂区域(7)接触的接触位置(CT)处,化学致密化的势垒层(16,30,38)为覆盖层 铜金属化(20,32,42)。 化学致密化的阻挡层(16,30,38)通过该结构的退火形成,以使杂质(14,28,36)与下面的耐熔金属基膜(12,34)反应; 杂质通过湿化学,等离子体轰击或结构退火的环境引入。

    Method of forming a metal conductor and diffusion layer
    8.
    发明授权
    Method of forming a metal conductor and diffusion layer 失效
    形成金属导体和扩散层的方法

    公开(公告)号:US5605724A

    公开(公告)日:1997-02-25

    申请号:US407353

    申请日:1995-03-20

    CPC分类号: H01L21/76856 H01L21/76843

    摘要: A method for minimizing reaction between metal conductors and other metals to minimize change in sheet resistance of the conductors upon heat treatment which includes providing a substrate. The substrate is preferably one of a dielectric, a metal or a semiconductor. A metallic diffusion barrier layer, preferably one of TiN, TiW or TiWN and preferably having a thickness of from about 10 nanometers to about 100 nanometers, is deposited on the substrate, preferably by one of sputtering, electron beam evaporation or chemical vapor deposition. The exposed surface of the metallic diffusion barrier layer is treated with a plasma, preferably an oxygen plasma, a nitrous oxide plasma or a plasma of an oxygen-containing species. An electrical conductor, preferably one of aluminum, aluminum-metal alloys, copper or copper-metal alloys and preferably having a thickness of from about 100 nanometers to about 1200 nanometers, is then deposited on the plasma-treated surface of the metallic diffusion barrier layer. The layers can be formed as one of a blanket or continuous films over the substrate. The conductor can then be patterned.

    摘要翻译: 一种用于使金属导体和其它金属之间的反应最小化的方法,以使热处理时导体的薄层电阻变化最小化,包括提供基板。 基板优选为电介质,金属或半导体中的一种。 优选通过溅射,电子束蒸发或化学气相沉积中的一种沉积在金属扩散阻挡层上,优选TiN,TiW或TiWN中的一种,优选具有约10纳米至约100纳米的厚度。 金属扩散阻挡层的暴露表面用等离子体,优选氧等离子体,一氧化二氮等离子体或含氧物质的等离子体进行处理。 然后将电导体(优选铝,铝 - 金属合金,铜或铜 - 金属合金中的一种)优选地具有约100纳米至约1200纳米的厚度,然后沉积在金属扩散阻挡层的等离子体处理的表面上 。 这些层可以形成为衬底上的覆盖层或连续膜之一。 然后可以对导体进行图案化。

    Method to improve the texture of aluminum metallization
    9.
    发明授权
    Method to improve the texture of aluminum metallization 失效
    改善铝金属化质地的方法

    公开(公告)号:US6077782A

    公开(公告)日:2000-06-20

    申请号:US23424

    申请日:1998-02-13

    摘要: A method to improve the texture of titanium and aluminum to reduce electromigration by controlling the deposition conditions and the texture of the substrates. Aluminum films can develop strong texture, when titanium is used underneath aluminum. However, to prevent the interaction between aluminum and titanium, a layer of TiN or other barrier is necessary. Fortunately, TiN has a similar atom arrangement on the plane as that of aluminum and titanium . Therefore, by controlling the orientation of titanium using a pre-sputter argon etch and low titanium deposition temperature, the texture of titanium can be transferred to TiN, and subsequently to aluminum.

    摘要翻译: 通过控制沉积条件和基板的质地,改善钛和铝的织构以减少电迁移的方法。 当铝在铝下使用时,铝膜可以发展出强烈的<111>质感。 然而,为了防止铝和钛之间的相互作用,需要一层TiN或其它屏障。 幸运的是,TiN在<111>平面上具有与铝<111>和钛<002>相似的原子排列。 因此,通过使用预溅射氩蚀刻和低钛沉积温度控制钛的取向,钛的织构可以转移到TiN,然后转移到铝。