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45 条记录 (耗时 0.032 秒)

    Variable doping of metal plugs for enhanced reliability
    2.
    发明授权
    Variable doping of metal plugs for enhanced reliability 有权
    金属插头的可变掺杂可提高可靠性

    公开(公告)号：US6130156A

    公开(公告)日：2000-10-10

    申请号：US281538

    申请日：1999-03-30

    申请人： Robert H. Havemann ,  Girish A. Dixit ,  Stephen W. Russell

    发明人： Robert H. Havemann ,  Girish A. Dixit ,  Stephen W. Russell

    IPC分类号： H01L23/52 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/441

    CPC分类号： H01L21/76843 ,  H01L21/76873 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76886 ,  H01L2221/1089 ,  H01L23/53219 ,  H01L23/53233 ,  H01L2924/0002

    摘要： A method of fabricating an interconnect wherein there is initially provided a first layer of electrically conductive interconnect (3). A via (7) is formed which is defined by walls extending to the first layer of interconnect. A layer of titanium (9) is formed between the electrically conductive interconnect and the first layer of electrically conductive metal (11). A first layer of electrically conductive metal is formed on the walls of the via having a predetermined etch rate relative to a specific etch species and a second layer of electrically conductive metal (13) is formed on the first layer of electrically conductive metal having an etch rate relative to the specific etch species greater than the first layer and which preferably extends into the via. The first layer of electrically conductive interconnect is preferably aluminum, the first layer of electrically conductive metal is preferably a metal containing from about one percent by weight to about one hundred percent copper and the rest essentially aluminum and the second layer of electrically conductive metal is preferably copper doped aluminum having a lower copper content than the first electrically conductive layer.

    摘要翻译： 一种制造互连的方法，其中最初提供第一层导电互连（3）。 形成通孔（7），其通过延伸到第一互连层的壁限定。 在导电互连和导电金属（11）的第一层之间形成一层钛（9）。 第一层导电金属形成在通孔的壁上，具有相对于特定蚀刻物质的预定蚀刻速率，并且第二层导电金属（13）形成在具有蚀刻的第一导电金属层上 相对于比第一层大的特定蚀刻物质的速率，并且优选地延伸到通孔中。 导电互连的第一层优选为铝，第一层导电金属优选为含有约1％至约100％铜的金属，其余基本上为铝，而第二层导电金属优选为 铜掺杂的铝的铜含量低于第一导电层。

    Hydrogen passivation of chemical-mechanically polished copper-containing layers
    3.
    发明授权
    Hydrogen passivation of chemical-mechanically polished copper-containing layers 有权
    化学机械抛光含铜层的氢钝化

    公开(公告)号：US06251771B1

    公开(公告)日：2001-06-26

    申请号：US09255466

    申请日：1999-02-22

    申请人： Patricia B. Smith ,  Girish A. Dixit ,  Eden Zielinski ,  Stephen W. Russell

    发明人： Patricia B. Smith ,  Girish A. Dixit ,  Eden Zielinski ,  Stephen W. Russell

    IPC分类号： H01L214763

    CPC分类号： H01L21/3212 ,  H01L21/321

    摘要： An embodiment of the instant invention is a method of forming an electronic device over a semiconductor substrate and having at least one level of metallic conductors, the method comprising the steps of: forming a dielectric layer over the semiconductor substrate, the dielectric layer having openings (step 102 of FIG. 1); forming a layer of the metallic conductor on the dielectric layer (step 104 of FIG. 1); removing a portion of the layer of the metallic conductor on the dielectric layer (step 106 of FIG. 1); and subjecting the exposed metallic conductor to a plasma which contains hydrogen or deuterium so as to passivate the metallic conductor (step 110 of FIG. 1). Preferably, the plasma contains a substance selected from the group consisting of: NH3, N2H2, H2S, and CH4, and the metallic conductors are comprised of a material selected from the group consisting of: copper, copper doped aluminum, Ag, Sn, Pb, Ti, Cr, Mg, Ta, and any combination thereof. The step of removing a portion of the layer of the metallic conductor is, preferably, performed by sputtering off a portion of the metallic conductor, chemical-mechanical polishing, etching, or a combination thereof.

    摘要翻译： 本发明的一个实施例是一种在半导体衬底上形成电子器件并具有至少一层金属导体的方法，该方法包括以下步骤：在半导体衬底上形成电介质层，电介质层具有开口（ 图1的步骤102）; 在介电层上形成金属导体层（图1的步骤104）; 去除介电层上的金属导体层的一部分（图1的步骤106）; 并将暴露的金属导体经受含有氢或氘的等离子体，以使金属导体钝化（图1的步骤110）。 优选地，等离子体包含选自由NH 3，N 2 H 2，H 2 S和CH 4组成的组的物质，金属导体由选自铜，铜掺杂的铝，Ag，Sn，Pb ，Ti，Cr，Mg，Ta及其任意组合。 优选地，通过溅射金属导体的一部分，化学机械抛光，蚀刻或其组合来去除金属导体的该层的一部分的步骤。

    Low pressure, low temperature, semiconductor gap filling process
    4.
    发明授权
    Low pressure, low temperature, semiconductor gap filling process 失效
    低压，低温，半导体缺口填充工艺

    公开(公告)号：US06333265B1

    公开(公告)日：2001-12-25

    申请号：US08766199

    申请日：1996-12-12

    申请人： Girish A. Dixit ,  Anthony Konecni ,  Robert H. Havemann

    发明人： Girish A. Dixit ,  Anthony Konecni ,  Robert H. Havemann

    IPC分类号： H01L2144

    CPC分类号： H01L21/76882 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76862

    摘要： A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;

    摘要翻译： 提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。 这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即， 〜3.0）。 优选地，空腔设置有不含钛的衬垫以促进空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地 在约100°-300℃的温度下不超过约30Mpa。以上述方式填充的空腔表现出比通过常规实践填充的结构小至多30％的电阻水平。

    Low pressure, low temperature, semiconductor gap filling process
    6.
    发明授权
    Low pressure, low temperature, semiconductor gap filling process 有权
    低压，低温，半导体缺口填充工艺

    公开(公告)号：US06589865B2

    公开(公告)日：2003-07-08

    申请号：US09899194

    申请日：2001-07-06

    申请人： Girish A. Dixit ,  Anthony Konecni ,  Robert H. Havemann

    发明人： Girish A. Dixit ,  Anthony Konecni ,  Robert H. Havemann

    IPC分类号： H01L214763

    CPC分类号： H01L21/76882 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76862

    摘要： A structure and process is provided for filling integrated circuit cavities such as contacts and vias. These structures are filled at relatively low temperatures of no more than about 300° C., and preferably between about 20°-275° C., which temperature range permits for the use of low dielectric constant (&kgr;) polymers (i.e., &kgr;

    摘要翻译： 提供了用于填充诸如触点和通孔的集成电路腔的结构和工艺。 这些结构在不超过约300℃，优选在约20°-275℃之间的较低温度下填充，该温度范围允许使用低介电常数（κ）聚合物（即， 〜3.0）。 优选地，空腔设置有元素的无钛衬里以便于空腔填充，并且空腔填充有CVD铝，其通过在大气压至约50MPa的压力下的强力填充物引入空腔中，并且优选地不 大约30MPa，在约100°-300℃的温度范围内。以上述方式填充的凹坑表现出比通过常规实践填充的结构低30％的电阻水平。

    Method and apparatus for reducing charge density on a dielectric coated substrate after exposure to a large area electron beam
    7.
    发明授权
    Method and apparatus for reducing charge density on a dielectric coated substrate after exposure to a large area electron beam 失效
    用于在暴露于大面积电子束之后降低电介质涂覆的基底上的电荷密度的方法和装置

    公开(公告)号：US07425716B2

    公开(公告)日：2008-09-16

    申请号：US11414649

    申请日：2006-04-27

    申请人： Alexandros T. Demos ,  Khaled A. Elsheref ,  Yuri Trachuk ,  Tom K. Cho ,  Girish A. Dixit ,  Hichem M'Saad ,  Derek Witty

    发明人： Alexandros T. Demos ,  Khaled A. Elsheref ,  Yuri Trachuk ,  Tom K. Cho ,  Girish A. Dixit ,  Hichem M'Saad ,  Derek Witty

    IPC分类号： H02H23/00

    CPC分类号： H01J37/317 ,  H01J2237/0041

    摘要： Embodiments in accordance with the present invention relate to a number of techniques, which may be applied alone or in combination, to reduce charge damage of substrates exposed to electron beam radiation. In one embodiment, charge damage is reduced by establishing a robust electrical connection between the exposed substrate and ground. In another embodiment, charge damage is reduced by modifying the sequence of steps for activating and deactivating the electron beam source to reduce the accumulation of charge on the substrate. In still another embodiment, a plasma is struck in the chamber containing the e-beam treated substrate, thereby removing accumulated charge from the substrate. In a further embodiment of the present invention, the voltage of the anode of the e-beam source is reduced in magnitude to account for differences in electron conversion efficiency exhibited by different cathode materials.

    摘要翻译： 根据本发明的实施例涉及可以单独或组合应用的多种技术，以减少暴露于电子束辐射的衬底的电荷损伤。 在一个实施例中，通过在暴露的基板和地之间建立牢固的电连接来减小电荷损伤。 在另一个实施例中，通过修改用于激活和去激活电子束源的步骤顺序来减少电荷损伤，以减少电荷在衬底上的累积。 在另一个实施例中，在包含电子束处理的衬底的室中撞击等离子体，从而从衬底去除积聚的电荷。 在本发明的另一个实施例中，电子束源的阳极的电压的大小被减小以考虑到由不同的阴极材料表现的电子转换效率的差异。

    Selective metal encapsulation schemes
    8.
    发明授权
    Selective metal encapsulation schemes 失效
    选择性金属封装方案

    公开(公告)号：US07205228B2

    公开(公告)日：2007-04-17

    申请号：US10812480

    申请日：2004-03-30

    申请人： Deenesh Padhi ,  Srinivas Gandikota ,  Mehul Naik ,  Suketu A. Parikh ,  Girish A. Dixit

    发明人： Deenesh Padhi ,  Srinivas Gandikota ,  Mehul Naik ,  Suketu A. Parikh ,  Girish A. Dixit

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76849 ,  H01L21/288 ,  H01L21/76829 ,  H01L21/7685 ,  H01L21/76885

    摘要： A method and system of processing a semiconductor substrate includes, in one or more embodiments, depositing a protective layer on the substrate surface comprising a conductive element disposed in a dielectric material; processing the protective layer to expose the conductive element; electrolessly depositing a metallic passivating layer onto the conductive element; and removing at least a portion of the protective layer from the substrate after electroless deposition. In another aspect, a method and system of processing a semiconductor includes depositing a metallic passivating layer onto a substrate surface comprising a conductive element, masking the passivating layer to protect the underlying conductive element of the substrate surface, removing the unmasked passivating layer, and removing the mask from the passivating layer.

    摘要翻译： 在一个或多个实施例中，处理半导体衬底的方法和系统包括在衬底表面上沉积保护层，所述保护层包括布置在电介质材料中的导电元件; 处理所述保护层以暴露所述导电元件; 将金属钝化层无电沉积到导电元件上; 以及在无电沉积之后从衬底去除保护层的至少一部分。 在另一方面，一种处理半导体的方法和系统包括在包括导电元件的衬底表面上沉积金属钝化层，掩蔽钝化层以保护衬底表面的下面的导电元件，去除未屏蔽的钝化层，以及去除 掩模从钝化层。