公开(公告)号：US20130277747A1

公开(公告)日：2013-10-24

申请号：US13454570

申请日：2012-04-24

申请人： Qing LIU ,  Nicolas LOUBET ,  Prasanna KHARE

发明人： Qing LIU ,  Nicolas LOUBET ,  Prasanna KHARE

IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L21/26593 ,  H01L21/266 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/66628 ,  H01L29/7849

摘要： An embodiment of a transistor includes a body and a semiconductor region configured to stress a portion of the body. For example, stressing a channel of the transistor may increase the mobility of carriers in the channel, and thus may reduce the “on” resistance of the transistor. For example, the substrate, source/drain regions, or both the substrate and source/drain regions of a PFET may be doped to compressively stress the channel so as to increase the mobility of holes in the channel. Or, the substrate, source/drain regions, or both the substrate and source/drain regions of an NFET may be doped to tensile stress the channel so as to increase the mobility of electrons in the channel.

摘要翻译： 晶体管的实施例包括主体和被配置为对身体的一部分施加应力的半导体区域。 例如，施加晶体管的沟道可以增加沟道中载流子的迁移率，从而可以降低晶体管的“导通”电阻。 例如，可以掺杂PFET的衬底，源极/漏极区域或者衬底和源/漏极区域，以对沟道进行压缩应力，从而增加沟道中空穴的迁移率。 或者，可以掺杂NFET的衬底，源极/漏极区域或衬底和源极/漏极区域两者以使通道拉伸应力，以增加沟道中电子的迁移率。

公开(公告)号：US20150340275A1

公开(公告)日：2015-11-26

申请号：US14425977

申请日：2012-09-05

申请人： Maud VINET ,  Nicolas LOUBET ,  Romain WACQUEZ

发明人： Maud VINET ,  Nicolas LOUBET ,  Romain WACQUEZ

IPC分类号： H01L21/762 ,  H01L21/8234 ,  H01L29/04 ,  H01L29/06 ,  H01L21/3065 ,  H01L21/311

CPC分类号： H01L21/76224 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/823481 ,  H01L29/04 ,  H01L29/045 ,  H01L29/0653 ,  H01L29/66772

摘要： A method of producing a microelectronic device in a substrate including a first semiconductor layer, a dielectric layer and a second monocrystalline semiconductor layer, the method including: etching a trench through the first semiconductor layer and the dielectric layer, and such that the trench delimits one active region of the microelectronic device; chemical vapor etching the second semiconductor layer, at a level of a bottom wall of the trench, according to at least two crystalline planes of the second semiconductor layer such that an etched part of the second semiconductor layer extends under a part of the active region; filling the trench and the etched part of the second semiconductor layer with a dielectric material.

摘要翻译： 一种在包括第一半导体层，电介质层和第二单晶半导体层的衬底中制造微电子器件的方法，所述方法包括：通过所述第一半导体层和所述介电层蚀刻沟槽，并且使得所述沟槽限定一个 微电子器件的有源区; 根据所述第二半导体层的至少两个晶面，使所述第二半导体层的蚀刻部分在所述有源区的一部分下方延伸，在所述沟槽的底壁的水平面刻蚀所述第二半导体层; 用介电材料填充沟槽和第二半导体层的蚀刻部分。