-
1.发明授权Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits 有权用于在超导体集成电路中通过接地平面边界进行信号传播的电容器公开(公告)号：US06777808B2
公开(公告)日：2004-08-17
申请号：US10293944
申请日：2002-11-12
IPC分类号： H01L2906
CPC分类号： H01L27/18 , H01L2924/0002 , H01L2924/00
摘要： The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
摘要翻译： 在超导体集成电路（图1）中与电容A52相关联的自感通过在电容器上方添加一层超导体金属（A54）来减少，有效地产生负电感以抵消电容器引线的自感， 从而降低电路的电感。 因此，可能通过电容器传输单通量量子（“SFQ”）脉冲。 上述类型的电容器（19和25图5）被并入超导集成电路SFQ传输线（图5）中，以允许SFQ脉冲的SQUID到SQUID传输，同时将相应SQUID的电路接地保持在DC 隔离。 偏置电流（10）可以连续地提供给多个SQUID（图1和图3，图7和图9），减少了先前为多个SQUID的操作所需的电源电流。
-
2.发明授权Capacitor for signal propagation across ground plane boundaries in superconductor integrated circuits 失效用于在超导体集成电路中通过接地平面边界进行信号传播的电容器公开(公告)号：US06518673B2
公开(公告)日：2003-02-11
申请号：US09882979
申请日：2001-06-15
IPC分类号： H01L2348
CPC分类号： H01L27/18 , H01L2924/0002 , H01L2924/00
摘要： The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.
摘要翻译： 在超导体集成电路（图1）中与电容A52相关联的自感通过在电容器上方添加一层超导体金属（A54）来减少，有效地产生负电感以抵消电容器引线的自感， 从而降低电路的电感。 因此，可能通过电容器传输单通量量子（“SFQ”）脉冲。 上述类型的电容器（19和25图5）被并入超导集成电路SFQ传输线（图5）中，以允许SFQ脉冲的SQUID到SQUID传输，同时将相应SQUID的电路接地保持在DC 隔离。 偏置电流（10）可以连续地提供给多个SQUID（图1和图3，图7和图9），减少了先前为多个SQUID的操作所需的电源电流。
-
公开(公告)号：US11569976B2
公开(公告)日：2023-01-31
申请号：US17340814
申请日：2021-06-07
IPC分类号： H04L7/00 , G06F13/40 , G06N10/00 , H03K19/195
摘要： One example includes an isochronous receiver system. The system includes a pulse receiver configured to receive an input data signal from a transmission line and to convert the input data signal to a pulse signal. The system also includes a converter system comprising a phase converter system. The phase converter system includes a plurality of pulse converters associated with a respective plurality of sampling windows across a period of an AC clock signal. At least two of the sampling windows overlap at any given phase of the AC clock signal, such that the converter system is configured to generate an output pulse signal that is phase-aligned with at least one of a plurality of sampling phases of the AC clock signal based on associating the pulse signal with at least two of the sampling windows.
-
公开(公告)号：US10984336B2
公开(公告)日：2021-04-20
申请号：US16529535
申请日：2019-08-01
申请人： Quentin P. Herr , Jonathan D. Egan
发明人： Quentin P. Herr , Jonathan D. Egan
IPC分类号： H01L29/06 , G06N10/00 , H03K19/195 , H01L39/22 , G06F1/06 , H01L39/24 , G06F1/12 , H01L39/02 , G06F1/10
摘要： One example includes a superconducting clock conditioning system. The system includes a plurality of inductive stages. Each of the plurality of inductive stages includes an inductive signal path that includes at least one inductor and a Josephson junction. The superconducting clock conditioning system is configured to receive an input AC clock signal and to output a conditioned AC clock signal having an approximately square-wave characteristic and having a peak amplitude that is less than a peak amplitude of the input AC clock signal.
-
公开(公告)号：US10103735B1
公开(公告)日：2018-10-16
申请号：US15684613
申请日：2017-08-23
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： H03K19/195 , H03K17/92
摘要： One example includes a superconducting gate system. The system includes a first input that is configured to provide a first input pulse and a second input that is configured to provide a second input pulse. The system also includes a gate configured to provide a first output pulse at a first output corresponding to a first logic function with respect to the first and second input pulses and based on a positive bias inductor and a first Josephson junction that are each coupled to the first output. The gate is also configured to provide a second output pulse at a second output corresponding to a second logic function with respect to the first and second input pulses and based on a negative bias inductor and a second Josephson junction that are each coupled to the second output.
-
公开(公告)号：US10102902B2
公开(公告)日：2018-10-16
申请号：US15714698
申请日：2017-09-25
IPC分类号： G11C11/44 , H03K3/38 , H03K19/195
摘要： One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.
-
公开(公告)号：US09780765B2
公开(公告)日：2017-10-03
申请号：US14564962
申请日：2014-12-09
申请人： Ofer Naaman , Quentin P. Herr
发明人： Ofer Naaman , Quentin P. Herr
CPC分类号： H03K3/38 , G06N99/002 , H01L39/223
摘要： One embodiment describes a Josephson current source system. The system includes a flux-shuttle loop that is inductively coupled with an AC input signal. The flux-shuttle loop includes a plurality of Josephson junctions spaced about the flux-shuttle loop and being configured, when activated, to sequentially trigger the plurality of Josephson junctions about the flux-shuttle loop in response to the AC input signal to generate a DC output current provided through an output inductor. The system also includes a flux injector that is configured to selectively activate and deactivate the flux-shuttle loop in response to an input signal to control an amplitude of the DC output current.
-
公开(公告)号：US09653153B2
公开(公告)日：2017-05-16
申请号：US15013687
申请日：2016-02-02
摘要： One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state. The memory cell also includes a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell. The memory cell further includes at least one Josephson junction configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state.
-
9.发明授权Superconducting phase-controlled hysteretic magnetic Josephson junction JMRAM memory cell 有权超导相控滞后磁约瑟夫逊结JMRAM记忆单元公开(公告)号：US09520181B1
公开(公告)日：2016-12-13
申请号：US14854994
申请日：2015-09-15
申请人： Donald L. Miller , Andrew Hostetler Miklich , Anna Y. Herr , Quentin P. Herr , William Robert Reohr
发明人： Donald L. Miller , Andrew Hostetler Miklich , Anna Y. Herr , Quentin P. Herr , William Robert Reohr
CPC分类号： G11C11/44 , G11C11/16 , G11C11/1673 , G11C11/1675
摘要： One embodiment describes a JMRAM memory cell system. The system includes a phase hysteretic magnetic Josephson junction (PHMJJ) that stores one of a first binary state and a second binary state in response to a write current provided during a data write operation and to provide a superconducting phase based on the stored digital state. The system also includes a directional write element configured to provide a directional bias current during the data write operation to provide the superconducting phase of the PHMJJ in a predetermined direction corresponding to the first binary state. The system further includes at least one Josephson junction having a critical current that is based on the superconducting phase of the PHMJJ and being configured to provide an output corresponding to the stored digital state in response to a read current that is provided during a read operation.
摘要翻译： 一个实施例描述了JMRAM存储器单元系统。 该系统包括相位滞后磁约瑟夫逊结（PHMJJ），其响应于在数据写入操作期间提供的写入电流而存储第一二进制状态和第二二进制状态之一，并且基于所存储的数字状态提供超导相位。 该系统还包括定向写入元件，其被配置为在数据写入操作期间提供方向偏置电流，以在对应于第一二进制状态的预定方向上提供PHMJJ的超导相位。 该系统还包括至少一个约瑟夫逊结，其具有基于PHMJJ的超导相位的临界电流，并且被配置为响应于在读取操作期间提供的读取电流来提供对应于存储的数字状态的输出。
-
公开(公告)号：US09466643B2
公开(公告)日：2016-10-11
申请号：US14482654
申请日：2014-09-10
CPC分类号： H01L27/18 , G11C11/44 , G11C19/32 , H01L39/025 , H01L39/22 , H01L39/223 , H01L39/24 , H03K19/195
摘要： One example includes a superconducting circuit. The circuit includes a plurality of layers comprising a first conductor layer and a second conductor layer overlying the first conductor layer, each of the first and second conductor layers comprising at least one signal element. The circuit also includes a ground grid that is conductively coupled to ground and comprises a first plurality of parallel ground lines that occupy the first conductor layer and extend in a first direction and a second plurality of parallel ground lines that occupy the second conductor layer and extend in a second direction that is orthogonal with respect to the first direction.
摘要翻译： 一个例子包括超导电路。 该电路包括多个层，包括第一导体层和覆盖第一导体层的第二导体层，第一和第二导体层中的每一个包括至少一个信号元件。 电路还包括导电耦合到地面的接地栅极，并且包括占据第一导体层并在第一方向上延伸的第一多个平行接地线和占据第二导体层并延伸的第二多个平行接地线的接地栅极 在相对于第一方向正交的第二方向上。
-
-
-
-
-
-
-
-
-
搜索结果
82 条记录 (耗时 0.024 秒)
