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公开(公告)号：US10102902B2
公开(公告)日：2018-10-16
申请号：US15714698
申请日：2017-09-25
IPC分类号： G11C11/44 , H03K3/38 , H03K19/195
摘要： One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.
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公开(公告)号：US10554207B1
公开(公告)日：2020-02-04
申请号：US16051058
申请日：2018-07-31
申请人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
发明人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
IPC分类号： H03K19/195 , H03K3/38 , G11C11/44 , G06N10/00
摘要： Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.
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公开(公告)号：US09812192B1
公开(公告)日：2017-11-07
申请号：US15351065
申请日：2016-11-14
IPC分类号： G11C11/44
CPC分类号： G11C11/44 , H03K3/38 , H03K19/195
摘要： One embodiment includes a superconducting gate memory circuit. The circuit includes a Josephson D-gate circuit configured to set a digital state as one of a first data state and a second data state in response to a write enable single flux quantum (SFQ) pulse provided on a write enable input and a respective presence of or absence of a write data SFQ pulse provided on a data write input. The circuit also includes a storage loop coupled to the Josephson D-gate. The storage loop can be configured to store the digital state and to readout the digital state at an output in response to a read enable SFQ pulse provided on a read enable input and a read data SFQ pulse provided on a read data input.
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公开(公告)号：US11159168B2
公开(公告)日：2021-10-26
申请号：US17094452
申请日：2020-11-10
申请人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
发明人： Anna Y. Herr , Quentin P. Herr , Ryan Edward Clarke , Harold Clifton Hearne, III , Alexander Louis Braun , Randall M. Burnett , Timothy Chi-Chao Lee
IPC分类号： H03K19/195 , G06N10/00 , G11C11/44 , H03K3/38
摘要： Non-destructive read out (NDRO) circuits are provided for use in reciprocal quantum logic (RQL) superconducting systems. Each NDRO circuit includes a “body” circuit that provides a single or multi-state sub-critical bias current to one or many independent “tail” circuitries. Each “tail” has minimal effect on the “body” thereby preventing any interference or destruction to the state of the “body” circuitry. The circuits reduce device count and thereby increase circuit density, simplify and reduce the cost of fabrication, and provide functionality not available in existing designs, such as the ability to write a state and read it in the same operation cycle. The NDRO circuits provide more compact unit cells useful in memory or logic arrays, demanding fewer resources with increased functionality. The circuits also provide compact cells for AND, AND-OR, A-NOT-B, inverter, multiplexer, and demultiplexer gates.
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公开(公告)号：US09876505B1
公开(公告)日：2018-01-23
申请号：US15256213
申请日：2016-09-02
IPC分类号： H03K19/195 , G06N99/00 , H04B1/40
CPC分类号： H03K19/195 , G06N99/002 , H03K3/38 , H03K19/1952 , H04B1/40
摘要： An isochronous receiver system is provided and includes a single flux quantum (SFQ) receiver to receive a data signal from a transmission line. The single flux quantum receiver then converts the data signal to an SFQ signal. The system also includes a converter system to convert the SFQ signal to a reciprocal quantum logic (RQL) signal and to phase-align the RQL signal with a sampling phase of an AC clock signal.
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公开(公告)号：US11569976B2
公开(公告)日：2023-01-31
申请号：US17340814
申请日：2021-06-07
IPC分类号： H04L7/00 , G06F13/40 , G06N10/00 , H03K19/195
摘要： One example includes an isochronous receiver system. The system includes a pulse receiver configured to receive an input data signal from a transmission line and to convert the input data signal to a pulse signal. The system also includes a converter system comprising a phase converter system. The phase converter system includes a plurality of pulse converters associated with a respective plurality of sampling windows across a period of an AC clock signal. At least two of the sampling windows overlap at any given phase of the AC clock signal, such that the converter system is configured to generate an output pulse signal that is phase-aligned with at least one of a plurality of sampling phases of the AC clock signal based on associating the pulse signal with at least two of the sampling windows.
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公开(公告)号：US10984336B2
公开(公告)日：2021-04-20
申请号：US16529535
申请日：2019-08-01
申请人： Quentin P. Herr , Jonathan D. Egan
发明人： Quentin P. Herr , Jonathan D. Egan
IPC分类号： H01L29/06 , G06N10/00 , H03K19/195 , H01L39/22 , G06F1/06 , H01L39/24 , G06F1/12 , H01L39/02 , G06F1/10
摘要： One example includes a superconducting clock conditioning system. The system includes a plurality of inductive stages. Each of the plurality of inductive stages includes an inductive signal path that includes at least one inductor and a Josephson junction. The superconducting clock conditioning system is configured to receive an input AC clock signal and to output a conditioned AC clock signal having an approximately square-wave characteristic and having a peak amplitude that is less than a peak amplitude of the input AC clock signal.
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公开(公告)号：US10103735B1
公开(公告)日：2018-10-16
申请号：US15684613
申请日：2017-08-23
申请人： Quentin P. Herr
发明人： Quentin P. Herr
IPC分类号： H03K19/195 , H03K17/92
摘要： One example includes a superconducting gate system. The system includes a first input that is configured to provide a first input pulse and a second input that is configured to provide a second input pulse. The system also includes a gate configured to provide a first output pulse at a first output corresponding to a first logic function with respect to the first and second input pulses and based on a positive bias inductor and a first Josephson junction that are each coupled to the first output. The gate is also configured to provide a second output pulse at a second output corresponding to a second logic function with respect to the first and second input pulses and based on a negative bias inductor and a second Josephson junction that are each coupled to the second output.
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公开(公告)号：US09780765B2
公开(公告)日：2017-10-03
申请号：US14564962
申请日：2014-12-09
申请人： Ofer Naaman , Quentin P. Herr
发明人： Ofer Naaman , Quentin P. Herr
CPC分类号： H03K3/38 , G06N99/002 , H01L39/223
摘要： One embodiment describes a Josephson current source system. The system includes a flux-shuttle loop that is inductively coupled with an AC input signal. The flux-shuttle loop includes a plurality of Josephson junctions spaced about the flux-shuttle loop and being configured, when activated, to sequentially trigger the plurality of Josephson junctions about the flux-shuttle loop in response to the AC input signal to generate a DC output current provided through an output inductor. The system also includes a flux injector that is configured to selectively activate and deactivate the flux-shuttle loop in response to an input signal to control an amplitude of the DC output current.
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公开(公告)号：US09653153B2
公开(公告)日：2017-05-16
申请号：US15013687
申请日：2016-02-02
摘要： One embodiment describes a memory cell. The memory cell includes a phase hysteretic magnetic Josephson junction (PHMJJ) that is configured to store one of a first binary logic state corresponding to a binary logic-1 state and a second binary logic state corresponding to a binary logic-0 state in response to a write current that is provided to the memory cell and to generate a superconducting phase based on the stored digital state. The memory cell also includes a superconducting read-select device that is configured to implement a read operation in response to a read current that is provided to the memory cell. The memory cell further includes at least one Josephson junction configured to provide an output based on the superconducting phase of the PHMJJ during the read operation, the output corresponding to the stored digital state.
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