公开(公告)号：US08332619B2

公开(公告)日：2012-12-11

申请号：US13314826

申请日：2011-12-08

申请人： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

发明人： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

摘要翻译： 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20110087867A1

公开(公告)日：2011-04-14

申请号：US12970040

申请日：2010-12-16

申请人： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

发明人： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

IPC分类号： G06F9/44

CPC分类号： G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

摘要翻译： 处理器可以包括地址监视器表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20120084536A1

公开(公告)日：2012-04-05

申请号：US13314826

申请日：2011-12-08

申请人： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

发明人： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

IPC分类号： G06F9/30

CPC分类号： G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

摘要翻译： 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US07882339B2

公开(公告)日：2011-02-01

申请号：US11165639

申请日：2005-06-23

申请人： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

发明人： Quinn A. Jacobson ,  Hong Wang ,  John Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant Bigbee ,  Shivnandan D. Kaushik

IPC分类号： G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  G06F15/00

CPC分类号： G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

摘要翻译： 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US20130073835A1

公开(公告)日：2013-03-21

申请号：US13675910

申请日：2012-11-13

申请人： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik

发明人： Quinn A. Jacobson ,  Hong Wang ,  John P. Shen ,  Gautham N. Chinya ,  Per Hammarlund ,  Xiang Zou ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik

IPC分类号： G06F9/30

CPC分类号： G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

摘要： A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction to write to a register of the state, an instruction to trigger the committing of buffered memory updates, an instruction to read the a status register of the state, and/or an instruction to clear one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

摘要翻译： 处理器可以包括地址监视表和原子更新表以支持推测性线程。 处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：写入状态寄存器的指令，触发提交缓冲存储器更新的指令，读取状态状态寄存器的指令和/或 指令清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

公开(公告)号：US07743233B2

公开(公告)日：2010-06-22

申请号：US11100032

申请日：2005-04-05

申请人： Hong Wang ,  Gautham N. Chinya ,  Richard A. Hankins ,  Shivnandan D. Kaushik ,  Bryant Bigbee ,  John Shen ,  Per Hammarlund ,  Xiang Zou ,  Jason W. Brandt ,  Prashant Sethi ,  Douglas M. Carmean ,  Baiju V. Patel ,  Scott Dion Rodgers ,  Ryan N. Rakvic ,  John L. Reid ,  David K. Poulsen ,  Sanjiv M. Shah ,  James Paul Held ,  James Charles Abel

发明人： Hong Wang ,  Gautham N. Chinya ,  Richard A. Hankins ,  Shivnandan D. Kaushik ,  Bryant Bigbee ,  John Shen ,  Per Hammarlund ,  Xiang Zou ,  Jason W. Brandt ,  Prashant Sethi ,  Douglas M. Carmean ,  Baiju V. Patel ,  Scott Dion Rodgers ,  Ryan N. Rakvic ,  John L. Reid ,  David K. Poulsen ,  Sanjiv M. Shah ,  James Paul Held ,  James Charles Abel

IPC分类号： G06F9/00

CPC分类号： G06F9/485 ,  G06F9/30043 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3891 ,  G06F9/461 ,  G06F9/4881

摘要： Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses or pages to actual sequencers or frames of the system. Rationing logic associated with the mapping manager may take into account sequencer attributes when such mapping is performed Relocation logic associated with the mapping manager may manage spill and fill of context information to/from a backing store when re-mapping actual sequencers. Sequencers may be allocated singly, or may be allocated as part of partitioned blocks. The mapping manager may also include translation logic that provides an identifier for the mapped sequencer each time a logical sequencer address is used in a user program. Other embodiments are also described and claimed.

摘要翻译： 公开了用于管理和转换逻辑定序器地址与多序列器多线程系统中的物理或逻辑顺控程序之间的映射的系统，方法和机制的实施例。 映射管理器可以管理逻辑顺控程序地址或页面到系统的实际定序器或帧的分配和映射。 与映射管理器相关联的配给逻辑可以在执行这样的映射时考虑定序器属性。当重新映射实际的定序器时，与映射管理器相关联的重定位逻辑可以管理向/从备份存储器的上下文信息的溢出和填充。 排序器可以单独分配，或者可以被分配为分区块的一部分。 映射管理器还可以包括每当在用户程序中使用逻辑定序器地址时为映射的定序器提供标识符的翻译逻辑。 还描述和要求保护其他实施例。

公开(公告)号：US20160019067A1

公开(公告)日：2016-01-21

申请号：US14866875

申请日：2015-09-26

申请人： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

发明人： Hong Wang ,  John P. Shen ,  Edward T. Grochowski ,  Richard A. Hankins ,  Gautham N. Chinya ,  Bryant E. Bigbee ,  Shivnandan D. Kaushik ,  Xiang Chris Zou ,  Per Hammarlund ,  Scott Dion Rodgers ,  Xinmin Tian ,  Anil Aggawal ,  Prashant Sethi ,  Baiju V. Patel ,  James P Held

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3867 ,  G06F9/30003 ,  G06F9/30043 ,  G06F9/3005 ,  G06F9/3009 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/3851 ,  G06F9/4843 ,  G06F9/4881

摘要： In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least 1) a field that makes reference to one or more instruction sequencers or 2) implicitly references with a pointer to code that specifically addresses one or more instruction sequencers when the code is executed.

公开(公告)号：US08010969B2

公开(公告)日：2011-08-30

申请号：US11151809

申请日：2005-06-13

申请人： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

发明人： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

IPC分类号： G06F3/00 ,  G06F9/46 ,  G06F7/38

CPC分类号： G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

摘要： A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

摘要翻译： 监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。 本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少 减少与用户级线程相关联的性能抑制事件。

公开(公告)号：US08887174B2

公开(公告)日：2014-11-11

申请号：US13191317

申请日：2011-07-26

申请人： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

发明人： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

IPC分类号： G06F3/00 ,  G06F11/34

CPC分类号： G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

摘要： A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

摘要翻译： 监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。 本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少 减少与用户级线程相关联的性能抑制事件。

公开(公告)号：US20120017221A1

公开(公告)日：2012-01-19

申请号：US13191317

申请日：2011-07-26

申请人： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

发明人： Richard A. Hankins ,  Gautham N. Chinya ,  Hong Wang ,  Shivnandan D. Kaushik ,  Bryant E. Bigbee ,  John P. Shen ,  Trung A. Diep ,  Xiang Zou ,  Baiju V. Patel ,  Paul M. Petersen ,  Sanjiv M. Shah ,  Ryan N. Rakvic ,  Prashant Sethi

IPC分类号： G06F9/46

CPC分类号： G06F11/3466 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88

摘要： A technique to monitor software thread performance and update software that issues or uses the thread(s) to reduce performance-inhibiting events. At least one embodiment of the invention uses hardware and/or software timers or counters to monitor various events associated with executing user-level threads and report these events back to a user-level software program, which can use the information to avoid or at least reduce performance-inhibiting events associated with the user-level threads.

摘要翻译： 监控软件线程性能和更新发布或使用线程以减少性能阻碍事件的软件的技术。 本发明的至少一个实施例使用硬件和/或软件定时器或计数器来监视与执行用户级线程相关联的各种事件并将这些事件报告回用户级软件程序，其可以使用该信息来避免或至少 减少与用户级线程相关联的性能抑制事件。