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    Trace design to minimize electromigration damage to solder bumps
    5.
    发明申请
    Trace design to minimize electromigration damage to solder bumps 有权
    跟踪设计，以尽量减少焊料凸块的电迁移损坏

    公开(公告)号：US20060186539A1

    公开(公告)日：2006-08-24

    申请号：US11047887

    申请日：2005-02-01

    申请人： Walter Dauksher ,  Wayne Richling ,  William Graupp

    发明人： Walter Dauksher ,  Wayne Richling ,  William Graupp

    IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

    CPC分类号： H01L24/10 ,  H01L23/66 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by introducing an intermediate trace routing design between the current delivering trace and the pad that distributes the inflow of current from the trace to multiple points of entry on the pad. The intermediate trace routing design includes an outer trace channel connected to the current delivering trace. A plurality of conductive trace leads connect the outer trace channel to the pad. Preferably, each of the plurality of conductive trace leads is characterized by a respective trace impedance so as to distribute equal current flow through each of the leads to the pad.

    摘要翻译： 设计方法通过寻求在集成电路焊盘和接头之间的界面处产生更均匀的电流分布，同时保持与标准集成电路设计一致的接口形式，从而减少集成电路接头（例如倒装芯片凸块）中的电迁移。 设计方法通过在当前传送跟踪和焊盘之间引入中间轨迹路由设计来解决焊盘上的当前分布，该焊盘将电流从轨迹流入到焊盘上的多个入口点。 中间轨迹路由设计包括连接到当前传送轨迹的外部跟踪通道。 多个导电迹线引线将外部迹线通道连接到该焊盘。 优选地，多个导电迹线引线中的每一个的特征在于相应的迹线阻抗，以便将相当的电流流经每个引线到达该焊盘。

    Trace Design to Minimize Electromigration Damage to Solder Bumps
    7.
    发明申请
    Trace Design to Minimize Electromigration Damage to Solder Bumps 有权
    追踪设计，以最大限度地减少焊接冲击的电迁移损坏

    公开(公告)号：US20080042271A1

    公开(公告)日：2008-02-21

    申请号：US11779833

    申请日：2007-07-18

    申请人： Walter Dauksher ,  Dennis Eaton

    发明人： Walter Dauksher ,  Dennis Eaton

    IPC分类号： H01L29/40

    CPC分类号： H01L24/10 ,  H01L23/66 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01023 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A design methodology reduces electromigration in integrated circuit joints such as flip-chip bumps by seeking to produce a more uniform current distribution at the interface between the integrated circuit pad and the joint while maintaining an interface form that coincides with standard integrated circuit designs is presented. The design methodology addresses the current distribution at the pad by dividing current carrying traces into a plurality of sub-traces with known resistances such that each sub-trace distributes a known amount of current to the pad of the integrated circuit. The multiple sub-traces connect to the pad and are placed to obtain a desired uniformity in the incoming current distribution. Width and/or length adjustments could be made to each of the plurality of sub-traces to obtain the desired resistances.

    摘要翻译： 设计方法通过寻求在集成电路焊盘和接头之间的界面处产生更均匀的电流分布，同时保持与标准集成电路设计一致的接口形式，从而减少集成电路接头（例如倒装芯片凸块）中的电迁移。 设计方法通过将载流迹线划分成具有已知电阻的多个子迹线来解决焊盘处的电流分布，使得每个子迹线将已知量的电流分配到集成电路的焊盘。 多个子迹线连接到焊盘并被放置以在输入电流分布中获得期望的均匀性。 可以对多个子迹线中的每一个进行宽度和/或长度调节以获得期望的电阻。