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公开(公告)号：US3179743A
公开(公告)日：1965-04-20
申请号：US19482762
申请日：1962-05-15
Applicant: RCA CORP
Inventor： AHRONS RICHARD W , BURNS JR LESLIE L
IPC: H04N5/57
CPC classification number: H04N5/57
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公开(公告)号：US3230391A
公开(公告)日：1966-01-18
申请号：US24342762
申请日：1962-12-10
Applicant: RCA CORP
Inventor： AHRONS RICHARD W
IPC: H03M7/00
CPC classification number: H03M7/003 , Y10S505/86
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公开(公告)号：US3555249A
公开(公告)日：1971-01-12
申请号：US3555249D
申请日：1967-12-28
Applicant: RCA CORP
Inventor： AHRONS RICHARD W
CPC classification number: H03K23/542
Abstract: A counter which is capable of counting in several closed-loop counting cycles and means for sensing certain bits which are of the same value at least once in all counting cycles for placing in the counter a count which is unique to only one of the counting cycles.
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4.发明授权Complementary semiconductor matrix arrays for low power dissipation logic application 失效用于低功耗逻辑应用的补充半导体矩阵阵列
公开(公告)号：US3550089A
公开(公告)日：1970-12-22
申请号：US3550089D
申请日：1968-10-17
Applicant: RCA CORP
Inventor： AHRONS RICHARD W
CPC classification number: G11C16/0466 , G11C17/06 , G11C17/08 , G11C17/12 , H03K19/17708
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公开(公告)号：US3009989A
公开(公告)日：1961-11-21
申请号：US80352259
申请日：1959-04-01
Applicant: RCA CORP
Inventor： AHRONS RICHARD W , BURNS JR LESLIE L , JOHNSTON LOREN B
IPC: H04N5/57
CPC classification number: H04N5/57
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Patent Agency Ranking
公开(公告)号：US3493786A
公开(公告)日：1970-02-03
申请号：US3493786D
申请日：1967-05-02
Applicant: RCA CORP
Inventor： AHRONS RICHARD W , KATZ STANLEY
IPC: G11C7/20 , G11C8/16 , G11C11/404 , H03K3/284 , H03K21/02
CPC classification number: G11C7/20 , G11C8/16 , G11C11/404
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公开(公告)号：US3372384A
公开(公告)日：1968-03-05
申请号：US35217764
申请日：1964-03-16
Applicant: RCA CORP
Inventor： AHRONS RICHARD W , CHRISTIANSEN DAVID A
IPC: G11C11/44
CPC classification number: G11C11/44 , Y10S505/837
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8.发明授权Flip-flop adaptable for counter comprising inverters and inhibitable gates and in cooperation with overlapping clocks for temporarily maintaining complementary outputs at same digital level 失效触发器适用于包括逆变器和可禁止门的计数器，并与重叠时钟配合，用于暂时维持相同数字电平的互补输出
公开(公告)号：US3322974A
公开(公告)日：1967-05-30
申请号：US53405866
申请日：1966-03-14
Applicant: RCA CORP
Inventor： AHRONS RICHARD W , STANLEY KATZ
CPC classification number: G11C19/28 , H03K3/356104 , H03K23/001 , H03K23/425
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9.发明授权Counter or shift register stage having both static and dynamic storage circuits 失效具有两个静态和动态存储电路的计数器或移位寄存器级
公开(公告)号：US3573498A
公开(公告)日：1971-04-06
申请号：US3573498D
申请日：1967-11-24
Applicant: RCA CORP
Inventor： AHRONS RICHARD W
CPC classification number: G11C19/184 , G11C19/28
Abstract: Signal translating stages which are useful in shift register applications are described. The signal translating stage is shown, in one example, to be constructed of complementary IGFET devices and, in another example, of single conductivity type IGFET devices. In either example, the shift register stage includes a flip-flop storage circuit and an inverter input capacitance node storage circuit which are operatively coupled and decoupled under the control of clock signals to translate information from the input to the output of the stage.
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公开(公告)号：US3562555A
公开(公告)日：1971-02-09
申请号：US3562555D
申请日：1967-09-01
Applicant: RCA CORP
Inventor： AHRONS RICHARD W
CPC classification number: G11C5/147 , G06F11/00 , G06F11/002 , G06F11/16
Abstract: A circuit for monitoring the power supply for a memory system which is arranged to inhibit operation of the memory system during a power supply failure while maintaining a temporary supply of power to the memory system.
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