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    Test method for delay circuit and test circuitry
    2.
    发明授权
    Test method for delay circuit and test circuitry 有权

    公开(公告)号：US12188982B2

    公开(公告)日：2025-01-07

    申请号：US17860216

    申请日：2022-07-08

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Kuo-Wei Chi ,  Chun-Chi Yu ,  Chih-Wei Chang

    IPC: G01R31/317 ,  H03K3/037 ,  H03K5/00 ,  H03K21/08

    Abstract: A test method for a delay circuit and a test circuitry are provided. The test circuitry incudes the delay circuit that essentially includes multiple serially connected logic gates, a clock pulse generator at an input end of the delay circuit for generating one or more cycles of clock signals, and a counter at an output end of the delay circuit for counting the clock signals passing through the delay circuit. The test circuitry implements a test mode by switching lines to the clock pulse generator and the counter. The test circuitry relies on a comparison result of a counting result made by the counter and a number of the cycles of the clock signals to test any failure of the delay circuit.

    MEMORY CONTROLLER AND MEMORY DATA RECEIVING METHOD
    3.
    发明申请
    MEMORY CONTROLLER AND MEMORY DATA RECEIVING METHOD 有权

    公开(公告)号：US20240402915A1

    公开(公告)日：2024-12-05

    申请号：US18665545

    申请日：2024-05-15

    Applicant: Realtek Semiconductor Corp.

    Inventor： Shih-Chang Chen ,  Chih-Wei Chang ,  Chun-Chi Yu

    IPC: G06F3/06

    Abstract: A memory controller is arranged to access a memory device, and includes a receiving circuit. The receiving circuit is arranged to receive a data signal and a data strobe signal from the memory device, and includes a sampling circuit and a comparison circuit. The sampling circuit is arranged to sample the data signal or a delayed data signal according to a plurality of delayed versions of the data strobe signal to generate a plurality of sampling values, wherein the delayed data signal is a delayed version of the data signal. The comparison circuit is arranged to compare the plurality of sampling values to obtain a comparison result, and arranged to determine to provide the data signal or the delayed data signal to the sampling circuit according to the comparison result.

    Memory controller and memory data receiving method for generate better sampling clock signal
    4.
    发明授权
    Memory controller and memory data receiving method for generate better sampling clock signal 有权

    公开(公告)号：US10916278B1

    公开(公告)日：2021-02-09

    申请号：US16575353

    申请日：2019-09-18

    Applicant: Realtek Semiconductor Corp.

    Inventor： Kuo-Wei Chi ,  Chun-Chi Yu ,  Chih-Wei Chang ,  Gerchih Chou ,  Shih-Chang Chen ,  Fu-Chin Tsai ,  Shih-Han Lin ,  Min-Han Tsai

    IPC: G11C7/22

    Abstract: A memory controller comprising: a delay circuit, configured to use a first delay value and a second delay value to respectively delay a sampling clock signal to generate a first and a second delayed sampling clock signal; a sampling circuit, configured to use a first edge of the first delayed sampling clock signal to sample a data signal to generate a first sampling value, and configured to use a second edge of the second delayed sampling clock signal to sample the data signal to generate a second sampling value; and a calibrating circuit, configured to generate a sampling delay value according to the first delay value based on the first sampling value and the second sampling value. The delay circuit uses the sampling delay value to generate an adjusted sampling clock signal and the sampling circuit sample the data signal by the adjusted sampling clock signal.

    Memory control circuit for adjusting reference voltage and associated memory control method
    5.
    发明授权
    Memory control circuit for adjusting reference voltage and associated memory control method 有权
    用于调整参考电压和相关存储器控制方法的存储器控​​制电路

    公开(公告)号：US09355708B2

    公开(公告)日：2016-05-31

    申请号：US14659629

    申请日：2015-03-17

    Applicant: Realtek Semiconductor Corp.

    Inventor： Chun-Chi Yu ,  Chih-Wei Chang ,  Shen-Kuo Huang

    IPC: G11C7/00 ,  G11C11/4091 ,  G11C11/4076

    CPC classification number: G11C11/4091 ,  G06F13/1689 ,  G11C7/1093 ,  G11C11/4076

    Abstract: A memory control circuit includes a comparator, an eye width measuring circuit and a calibration circuit, wherein the comparator is arranged to compare a data signal with a reference voltage to generate a compared data signal; the eye width measuring circuit is coupled to the comparator, and is arranged to measure an eye width of the compared data signal to generate a measuring result; and the calibration circuit is coupled to the comparator and the eye width measuring circuit, and is arranged to adjust a level of the reference voltage according to the measuring result.

    Abstract translation: 存储器控制电路包括比较器，眼睛宽度测量电路和校准电路，其中比较器被布置为将数据信号与参考电压进行比较以产生比较的数据信号; 眼宽测量电路耦合到比较器，并且被布置成测量比较数据信号的眼睛宽度以产生测量结果; 并且校准电路耦合到比较器和眼睛宽度测量电路，并且被布置为根据测量结果来调整参考电压的电平。

    Electronic package structure with a core ground wire and chip thereof
    6.
    发明授权
    Electronic package structure with a core ground wire and chip thereof 有权

    公开(公告)号：US11264352B2

    公开(公告)日：2022-03-01

    申请号：US16897424

    申请日：2020-06-10

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Ting-Ying Wu ,  Chien-Hsiang Huang ,  Chin-Yuan Lo ,  Chih-Wei Chang

    IPC: H01L23/00

    Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

    Memory controller and method for calibrating data reception window
    7.
    发明公开
    Memory controller and method for calibrating data reception window 审中-公开

    公开(公告)号：US20230307038A1

    公开(公告)日：2023-09-28

    申请号：US18119808

    申请日：2023-03-09

    Applicant: Realtek Semiconductor Corp.

    Inventor： Shih-Chang Chen ,  Chih-Wei Chang ,  Chun-Chi Yu

    IPC: G11C11/4099 ,  G11C11/4072

    CPC classification number: G11C11/4099 ,  G11C11/4072

    Abstract: A method for calibrating a data reception window includes: (A) setting a level of a reference voltage by different predetermined values and repeatedly sampling a data signal to obtain multiple first valid data reception windows; (B) establishing a first eye diagram based on the first valid data reception windows; (C) resetting the level of the reference voltage by the predetermined values combined with a first offset and repeatedly sampling the data signal according to the reference voltage to obtain multiple second valid data reception windows and (D) selectively updating the first eye diagram according to the second valid data reception windows. When width of a second valid data reception window is greater than width of a first valid data reception window corresponding to the same predetermined value, the first valid data reception window in the first eye diagram is replaced by the second valid data reception window.

    Detection circuit and detection method
    8.
    发明授权
    Detection circuit and detection method 有权

    公开(公告)号：US11315656B1

    公开(公告)日：2022-04-26

    申请号：US17182324

    申请日：2021-02-23

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Shih-Han Lin ,  Chun-Chi Yu ,  Chih-Wei Chang ,  Gerchih Chou ,  Shih-Chang Chen ,  Kuo-Wei Chi ,  Fu-Chin Tsai ,  Min-Han Tsai

    IPC: G11C29/00 ,  G11C29/50 ,  G11C11/401

    Abstract: A detection circuit and a detection method are provided. The detection circuit is suitable for a system-on-chip (SoC). The SoC is coupled to an alarm pin of a DDR4 memory through a connection pad, and the detection circuit includes a control circuit coupled to the connection pad. In response to the DDR4 memory performing a refresh process or a specific event occurring, the control circuit outputs a test signal with a first voltage level to the connection pad, and determines whether a voltage level of the connection pad is tied to a second voltage level. In response to determining that the voltage level of the connection pad is tied to the second voltage level, the control circuit outputs an interrupt signal to a CPU of the SoC, and the interrupt signal indicates that the alarm pin of the DDR4 memory is not controlled normally by the DDR4 memory.

    MEMORY CONTROL CIRCUIT AND ASSOCIATED MEMORY CONTROL METHOD
    10.
    发明申请
    MEMORY CONTROL CIRCUIT AND ASSOCIATED MEMORY CONTROL METHOD 有权
    存储器控制电路和相关的存储器控​​制方法

    公开(公告)号：US20160035411A1

    公开(公告)日：2016-02-04

    申请号：US14659629

    申请日：2015-03-17

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Chun-Chi Yu ,  Chih-Wei Chang ,  Shen-Kuo Huang

    IPC: G11C11/4091 ,  G11C11/4076

    CPC classification number: G11C11/4091 ,  G06F13/1689 ,  G11C7/1093 ,  G11C11/4076

    Abstract: a memory control circuit includes a comparator, an eye width measuring circuit and a calibration circuit, wherein the comparator is arranged to compare a data signal with a reference voltage to generate a compared data signal; the eye width measuring circuit is coupled to the comparator, and is arranged to measure an eye width of the compared data signal to generate a measuring result; and the calibration circuit is coupled to the comparator and the eye width measuring circuit, and is arranged to adjust a level of the reference voltage according to the measuring result.

    Abstract translation: 存储器控制电路包括比较器，眼睛宽度测量电路和校准电路，其中所述比较器被布置为将数据信号与参考电压进行比较以产生比较的数据信号; 眼宽测量电路耦合到比较器，并且被布置成测量比较数据信号的眼睛宽度以产生测量结果; 并且校准电路耦合到比较器和眼睛宽度测量电路，并且被布置为根据测量结果来调整参考电压的电平。

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