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    METHOD FOR PERFORMING MEMORY CALIBRATION, ASSOCIATED SYSTEM ON CHIP INTEGRATED CIRCUIT AND NON-TRANSITORY COMPUTER-READABLE MEDIUM
    1.
    发明申请
    METHOD FOR PERFORMING MEMORY CALIBRATION, ASSOCIATED SYSTEM ON CHIP INTEGRATED CIRCUIT AND NON-TRANSITORY COMPUTER-READABLE MEDIUM 有权

    公开(公告)号：US20220238149A1

    公开(公告)日：2022-07-28

    申请号：US17515571

    申请日：2021-11-01

    Applicant: Realtek Semiconductor Corp.

    Inventor： Tse-Yi Hsieh ,  Ting-Ying Wu ,  Shu-Min Wu

    IPC: G11C11/4072 ,  G11C11/4096

    Abstract: A method for performing memory calibration and an associated System on Chip (SoC) Integrated Circuit (IC) are provided. The method may include: in a power-up and initialization phase, controlling a physical layer (PHY) circuit within the SoC IC to apply power to a memory through a pad set and perform initialization on the memory; in an impedance-calibration-related phase, triggering the memory to perform impedance calibration regarding a set of data pins; in at least one subsequent phase, during performing any calibration operation among a reading-related calibration operation and a writing-related calibration operation, performing a data access test corresponding to a set of test points on a predetermined mask, wherein the predetermined mask is movable with respect to a data eye; and according to whether the data access test is successful, selectively stopping the any calibration operation.

    ELECTRONIC DEVICE TEST METHOD AND TEST DEVICE
    4.
    发明申请
    ELECTRONIC DEVICE TEST METHOD AND TEST DEVICE 有权

    公开(公告)号：US20230132675A1

    公开(公告)日：2023-05-04

    申请号：US17978228

    申请日：2022-11-01

    Applicant: Realtek Semiconductor Corp.

    Inventor： Han-Yun Tsai ,  Shih-Hung Wang ,  Ting-Ying Wu

    IPC: G01R31/3183 ,  G11C7/10

    Abstract: An electronic system test method, comprising: (a)inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b)acquiring a output response corresponding to the step (a); and (c)after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

    Electronic package structure with a core ground wire and chip thereof
    5.
    发明授权
    Electronic package structure with a core ground wire and chip thereof 有权

    公开(公告)号：US11264352B2

    公开(公告)日：2022-03-01

    申请号：US16897424

    申请日：2020-06-10

    Applicant: REALTEK SEMICONDUCTOR CORP.

    Inventor： Ting-Ying Wu ,  Chien-Hsiang Huang ,  Chin-Yuan Lo ,  Chih-Wei Chang

    IPC: H01L23/00

    Abstract: An electronic package structure and a chip thereof are provided. The electronic package structure includes a substrate, a chip, a plurality of signal wires, and a core ground wire. The chip disposed on and electrically connected to the substrate has a core wiring region and an input and output pad region located at a top surface thereof. The input and output pad region is located between the core wiring region and an edge of the chip. The chip includes a plurality of signal pads in the input and output region and a core ground pad adjacent to one of the signal pads. The core ground pad located in the core wiring region. The signal wires are respectively connected to the signal pads. The core ground wire connected to the core ground pad is adjacent to and shields one of the signal wires.

    Electronic device test method and test device
    6.
    发明授权
    Electronic device test method and test device 有权

    公开(公告)号：US11994558B2

    公开(公告)日：2024-05-28

    申请号：US17978228

    申请日：2022-11-01

    Applicant: Realtek Semiconductor Corp.

    Inventor： Han-Yun Tsai ,  Shih-Hung Wang ,  Ting-Ying Wu

    IPC: G06F11/10 ,  G01R31/3183 ,  G11C7/10 ,  H01L23/00 ,  H01L23/538 ,  H03M13/00 ,  H03M13/29

    CPC classification number: G01R31/318328 ,  G11C7/1072

    Abstract: An electronic system test method, comprising: (a) inputting a victim test pattern to a victim signal path of a target electronic system and simultaneously inputting at least one aggressor test pattern to at least one aggressor signal path of the target electronic system, according to a major set of test patterns comprising a plurality of minor set of test patterns; (b) acquiring a output response corresponding to the step (a); and (c) after changing the victim test pattern or the aggressor test pattern, and after repeating the step (a) and the step (b) until all of the major test patterns set are used thereby acquiring a plurality of the output responses, determining a combination level according to the output responses. The victim test pattern is an X bit pattern and the aggressor test pattern is a Y bit pattern, X and Y are positive integers larger than or equal to 3.

    METHOD FOR SIMULATING SYSTEM AND ASSOCIATED ELECTRONIC DEVICE
    8.
    发明公开
    METHOD FOR SIMULATING SYSTEM AND ASSOCIATED ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230244843A1

    公开(公告)日：2023-08-03

    申请号：US18098674

    申请日：2023-01-18

    Applicant: Realtek Semiconductor Corp.

    Inventor： Shih-Hung Wang ,  Chia-Lin Tu ,  Ting-Ying Wu

    IPC: G06F30/367 ,  G06F1/18

    CPC classification number: G06F30/367 ,  G06F1/189

    Abstract: The present invention provides an electronic device including a storage device and a processor. The storage device includes a program code and a database, wherein the database includes a plurality of combinations of printed circuit boards and packages and a plurality of channel models. The processor is configured to execute the program code to perform the steps of: obtaining a first combination of the plurality of combinations of printed circuit boards and packages from the database; obtaining a first channel model of the plurality of channel models from the database, wherein the first channel model is generated according to the first combination; determining first die information; and performing simulation to generate characteristics of a power delivery network and a voltage drop of a system according to the first channel model and the first die information.

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