公开(公告)号：US20160021745A1

公开(公告)日：2016-01-21

申请号：US14800751

申请日：2015-07-16

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： TING-YING WU ,  CHENG-LIN WU ,  CHIN-YUAN LO ,  WEN-SHAN WANG

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L2924/0002 ,  H05K1/0215 ,  H05K1/0289 ,  H05K2201/10159 ,  H05K2201/10704 ,  H05K2201/10712 ,  H05K2201/10719 ,  H05K2201/10734 ,  Y02P70/613 ,  H01L2924/00

Abstract: A Ball Grid Array (BGA) formed on printed circuit board is provided. The BGA comprises a first solder ball module and a second solder ball module. The first solder ball module comprises a plurality of first solder balls, wherein one of the first solder balls is grounded for shielding two other first solder balls, and one of the first solder balls is floating. The second solder ball module comprises a plurality of second solder balls, wherein two of the second solder balls are grounded and one of the two grounded second solder balls penetrates the printed circuit board through a plated through hole formed on the printed circuit board for shielding two first solder balls among the first solder balls.

Abstract translation: 提供了一种形成在印刷电路板上的球栅阵列（BGA）。 BGA包括第一焊球模块和第二焊球模块。 第一焊球模块包括多个第一焊球，其中第一焊球之一接地以屏蔽两个其它第一焊球，并且第一焊球中的一个浮动。 第二焊球模块包括多个第二焊球，其中两个第二焊球接地，并且两个接地的第二焊球中的一个通过形成在印刷电路板上的电镀通孔穿透印刷电路板，用于屏蔽两个 第一焊球之间的第一焊球。

公开(公告)号：US20240379152A1

公开(公告)日：2024-11-14

申请号：US18368602

申请日：2023-09-15

Applicant: REALTEK SEMICONDUCTOR CORP.

Inventor： MING-SHENG PENG ,  TING-YING WU ,  SHIH-HUNG WANG ,  WEI-ZHI CHEN

IPC: G11C11/4093 ,  G11C29/54 ,  H03K19/00

Abstract: A signal quality optimization system and a signal quality optimization method are provided. The method includes: executing a ZQ calibration process on an off-chip driver (OCD) circuit of a first circuit and an on-die termination (ODT) circuit of a second circuit to obtain calibrated resistor quantities; performing a waveform test process, including: setting a predetermined time rule to determine an operation success condition, adjusting the OCD circuit according to the calibration calibrated quantity corresponding to a target ODT resistance, obtaining a signal eye diagram, and obtaining an adjustable resistor ratio by performing adjustments and tests; extracting the OCD resistance value with the highest adjustable resistor ratio to obtain preferred ODT-OCD resistance combinations; and configuring the ODT circuit and the OCD circuit according to the preferred ODT-OCD resistance combinations, and testing the preferred ODT-OCD resistance combinations to obtain an optimized ODT-OCD resistance combination according to test results.