公开(公告)号：US20210184054A1

公开(公告)日：2021-06-17

申请号：US16951692

申请日：2020-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hironobu MIYAMOTO ,  Masami SAWADA ,  Tatsuya USAMI ,  Tomoo NAKAYAMA

IPC: H01L29/861 ,  H01L29/24 ,  H01L29/66

Abstract: A gallium oxide diode includes: a gallium oxide substrate having an n-type gallium oxide drift layer; an anode electrode of a metal film formed over a front surface of the n-type gallium oxide drift layer; a cathode electrode formed over a rear surface of the gallium oxide substrate; and a reaction layer of a metal oxide film of p-type conductivity formed between the anode electrode and the n-type gallium oxide drift layer. Further, a manufacturing method of a gallium oxide diode includes steps of forming an anode electrode of a metal film over an n-type gallium oxide drift layer formed over a gallium oxide substrate; and forming a reaction layer between the anode electrode and the n-type gallium oxide drift layer by performing a heat treatment to the gallium oxide substrate after forming the anode electrode, the reaction layer being made of a metal oxide film with p-type conductivity.

公开(公告)号：US20230411512A1

公开(公告)日：2023-12-21

申请号：US18189541

申请日：2023-03-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Akihiro SHIMOMURA ,  Masami SAWADA

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/66734

Abstract: An improved structure and a manufacturing method of a vertical type power MOSFET having a super junction configuration is disclosed. The improved structure and the manufacturing method of the vertical type power MOSFET comprising: a step of preparing a semiconductor substrate SB including an n-type semiconductor layer SL and a p-type epitaxial layer EP on the semiconductor layer SL; a step of forming a trench GT in the p-type epitaxial layer EP by using an etching mask with a predetermined opening width; and a step of introducing an n-type impurity into a bottom portion of the trench GT using the etching mask with the predetermined opening width, whereby forming an n-type column NC at the bottom of trench GT and reaching the semiconductor layer SL.

公开(公告)号：US20230039359A1

公开(公告)日：2023-02-09

申请号：US17838707

申请日：2022-06-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Masami SAWADA

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L29/66

Abstract: Variations of characteristics of a semiconductor device provided with a power MOSFET having a super junction structure are suppressed, and reliability of the semiconductor device is improved. A trench embedding an insulating film, which constitutes an insulator column therein, is formed in a first main surface of a semiconductor substrate whose crystal plane is a (110) plane. A crystal plane of a side surface of the trench in a short-side direction is a (111) plane, and a p-type diffusion layer constituting a p-column is formed in the above-mentioned side surface.

公开(公告)号：US20210217844A1

公开(公告)日：2021-07-15

申请号：US17115204

申请日：2020-12-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Hiroshi YANAGIGAWA ,  Katsumi EIKYU ,  Masami SAWADA ,  Akihiro SHIMOMURA ,  Kazuhisa MORI

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66

Abstract: In a trench gate type power MOSFET having a super-junction structure, both improvement of a breakdown voltage of a device and reduction of on-resistance are achieved. The trench gate and a column region are arranged so as to be substantially orthogonal to each other in a plan view, and a base region (channel forming region) and the column region are arranged separately in a cross-sectional view.

公开(公告)号：US20230029438A1

公开(公告)日：2023-01-26

申请号：US17828349

申请日：2022-05-31

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Masami SAWADA

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66

Abstract: Reliability of a semiconductor device is improved by suppressing occurrence of variation in characteristics of the semiconductor device provided with a power MOSFET that has a super junction structure. A fixed charge layer FC is formed in a trench T2 that is formed in an upper surface of a semiconductor substrate SB and is adjacent to a p type body region BD and an n type drift layer DL. The fixed charge layer FC constituting a p column accumulates holes in the semiconductor substrate SB located at a side surface of the trench T2 to form a hole accumulation region HC.

公开(公告)号：US20220238651A1

公开(公告)日：2022-07-28

申请号：US17553251

申请日：2021-12-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yasutaka NAKASHIBA ,  Akihiro SHIMOMURA ,  Masami SAWADA

IPC: H01L29/08 ,  H01L29/78 ,  H01L23/495 ,  H01L23/00

Abstract: The semiconductor device according to one embodiment includes a semiconductor substrate having a first surface and a second surface on an opposite side of the first surface, a gate insulating film formed on the first surface, a gate formed on the first surface via the gate insulating film, a source region formed in the first surface side of the semiconductor substrate, a body region formed so as to be in contact with the source region and including a channel region, a drain region formed in the second surface side of the semiconductor substrate, and a drift region formed so as to be in contact with the second surface side of the body region and the first surface side of the drain region. The semiconductor substrate has at least one concave portion formed in the second surface and being recessed toward the first surface.

公开(公告)号：US20210028082A1

公开(公告)日：2021-01-28

申请号：US15931230

申请日：2020-05-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya USAMI ,  Hironobu MIYAMOTO ,  Masami SAWADA

IPC: H01L23/367 ,  H01L23/373 ,  H01L29/24 ,  H01L29/20 ,  H01L29/16

Abstract: A Semiconductor device includes a substrate and a thermal conductive film. The substrate has a top surface and a back surface which oppose with each other. A first opening is formed on the back surface of substrate. The thermal conductive film includes a first thermal conductive portion formed in the first opening. The first thermal conductive portion is embedded in the first opening such that a void is formed in the first opening.