公开(公告)号：US20150102421A1

公开(公告)日：2015-04-16

申请号：US14579898

申请日：2014-12-22

Applicant: Renesas Electronics Corporation

Inventor： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC: H01L27/11 ,  G06F17/50

CPC classification number: H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

Abstract translation: 一种具有SRAM的半导体器件，包括：第一晶体管和第五晶体管设置在其中的单片第一有源区; 与第一有源区分离的第二有源区，其中设置第二晶体管; 其中设置第三晶体管和第六晶体管的单片第三有源区; 以及与第三有源区分离的第四有源区，其中设置第四晶体管。 每个驱动晶体管分为第一晶体管和第二晶体管（或第三晶体管和第四晶体管），并且这些驱动晶体管设置在不同的有源区域上。

公开(公告)号：US10304526B2

公开(公告)日：2019-05-28

申请号：US16059255

申请日：2018-08-09

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

IPC: G11C5/14 ,  G11C11/417 ,  G11C5/06 ,  G11C11/413 ,  H01L27/092 ,  H01L27/11

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

公开(公告)号：US10079055B2

公开(公告)日：2018-09-18

申请号：US15648702

申请日：2017-07-13

Applicant: Renesas Electronics Corporation

Inventor： Shigenobu Komatsu ,  Masanao Yamaoka ,  Noriaki Maeda ,  Masao Morimoto ,  Yasuhisa Shimazaki ,  Yasuyuki Okuma ,  Toshiaki Sano

IPC: G11C5/14 ,  G11C11/417 ,  H01L27/11 ,  G11C5/06 ,  G11C11/413 ,  H01L27/092

CPC classification number: G11C11/417 ,  G11C5/06 ,  G11C5/14 ,  G11C11/413 ,  H01L27/092 ,  H01L27/1104

Abstract: A semiconductor integrated circuit which can respond to changes of the amount of retained data at the time of standby is provided. The semiconductor integrated circuit comprises a logic circuit (logic) and plural SRAM modules. The plural SRAM modules perform power control independently of the logic circuit, and an independent power control is performed among the plural SRAM modules. Specifically, one terminal and the other terminal of a potential control circuit of each SRAM module are coupled to a cell array and a local power line, respectively. The local power line of one SRAM module and the local power line of the other SRAM module share a shared local power line. A power switch of one SRAM module and a power switch of the other SRAM module are coupled in common to the shared local power line.

公开(公告)号：US09196622B2

公开(公告)日：2015-11-24

申请号：US14579898

申请日：2014-12-22

Applicant: Renesas Electronics Corporation

Inventor： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC: H01L27/11 ,  H01L27/02 ,  G11C11/412 ,  G06F17/50

CPC classification number: H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

Abstract translation: 一种具有SRAM的半导体器件，包括：第一晶体管和第五晶体管设置在其中的单片第一有源区; 与第一有源区分离的第二有源区，其中设置第二晶体管; 其中设置第三晶体管和第六晶体管的单片第三有源区; 以及与第三有源区分离的第四有源区，其中设置第四晶体管。 每个驱动晶体管分为第一晶体管和第二晶体管（或第三晶体管和第四晶体管），并且这些驱动晶体管设置在不同的有源区域上。

公开(公告)号：US09123435B2

公开(公告)日：2015-09-01

申请号：US13874834

申请日：2013-05-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC: G11C11/00 ,  G11C11/412 ,  G11C5/06 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US10510400B2

公开(公告)日：2019-12-17

申请号：US15957263

申请日：2018-04-19

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki Sano ,  Ken Shibata ,  Shinji Tanaka ,  Makoto Yabuuchi ,  Noriaki Maeda

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/12 ,  G11C11/418 ,  G11C8/16 ,  G11C11/412

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

公开(公告)号：US10483268B2

公开(公告)日：2019-11-19

申请号：US16123396

申请日：2018-09-06

Applicant: Renesas Electronics Corporation

Inventor： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC: H01L27/092 ,  H01L27/11 ,  H01L27/02 ,  G11C11/412 ,  G06F17/50 ,  H01L23/528

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

公开(公告)号：US09704873B2

公开(公告)日：2017-07-11

申请号：US15165651

申请日：2016-05-26

Applicant: Renesas Electronics Corporation

Inventor： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC: H01L27/092 ,  H01L27/11 ,  H01L27/02 ,  G11C11/412 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.

公开(公告)号：US09349438B2

公开(公告)日：2016-05-24

申请号：US14658163

申请日：2015-03-14

Applicant: Renesas Electronics Corporation

Inventor： Toshiaki Sano ,  Ken Shibata ,  Shinji Tanaka ,  Makoto Yabuuchi ,  Noriaki Maeda

IPC: G11C7/00 ,  G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C8/16 ,  G11C11/412 ,  G11C11/418

Abstract: A semiconductor storage device provided can increase a write margin and suppress increase of a chip area. The semiconductor storage device includes plural memory cells arranged in a matrix; plural bit-line pairs arranged corresponding to each column of the memory cells; a write driver circuit which transmits data to a bit-line pair of a selected column according to write data; and a write assist circuit which drives a bit line on a low potential side of the bit-line pair of a selected column to a negative voltage level. The write assist circuit includes first signal wiring; a first driver circuit which drives the first signal wiring according to a control signal; and second signal wiring which is coupled to the bit line on the low-potential side and generates a negative voltage by the driving of the first driver circuit, based on inter-wire coupling capacitance with the first signal wiring.

Abstract translation: 提供的半导体存储装置可以增加写入裕度并抑制芯片面积的增加。 半导体存储装置包括以矩阵形式布置的多个存储单元; 对应于存储器单元的每列布置的多个位线对; 写入驱动器电路，根据写入数据将数据发送到所选列的位线对; 以及将所选列的位线对的低电位侧的位线驱动到负电压电平的写辅助电路。 写辅助电路包括第一信号线; 第一驱动电路，其根据控制信号驱动第一信号布线; 以及第二信号布线，其通过与第一信号布线的线间耦合电容通过第一驱动电路的驱动而耦合到低电位侧的位线并产生负电压。

公开(公告)号：US20160043091A1

公开(公告)日：2016-02-11

申请号：US14921038

申请日：2015-10-23

Applicant: Renesas Electronics Corporation

Inventor： Masao Morimoto ,  Noriaki Maeda ,  Yasuhisa Shimazaki

IPC: H01L27/11 ,  H01L27/02

CPC classification number: H01L27/1116 ,  G06F17/5072 ,  G11C11/412 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0928 ,  H01L27/1104

Abstract: A semiconductor device having an SRAM which includes: a monolithic first active region in which a first transistor and a fifth transistor are disposed; a second active region separated from the first active region, in which a second transistor is disposed; a monolithic third active region in which a third transistor and a sixth transistor are disposed; and a fourth active region separated from the third active region, in which a fourth transistor is disposed. Each driver transistor is divided into a first transistor and a second transistor (or a third transistor and a fourth transistor) and these driver transistors are disposed over different active regions.