公开(公告)号：US09256261B2

公开(公告)日：2016-02-09

申请号：US13903535

申请日：2013-05-28

Applicant: Renesas Electronics Corporation

Inventor： Masanori Isoda ,  Hidehiro Fujiwara ,  Koji Nii

IPC: G06F1/26 ,  G06F3/00 ,  G06F12/00 ,  G06F11/00 ,  G06F21/44 ,  G11C5/14 ,  G11C8/20 ,  G11C11/417 ,  G06F11/22 ,  G06F21/71 ,  G06F12/14 ,  G06F21/78

CPC classification number: G06F1/26 ,  G06F11/2247 ,  G06F12/14 ,  G06F21/44 ,  G06F21/71 ,  G06F21/78 ,  G06F2212/1052 ,  G11C5/14 ,  G11C8/20 ,  G11C11/417

Abstract: A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.

Abstract translation: 一种半导体器件包括具有其输出电压由控制信号控制的电源控制电路的识别信息产生电路和具有第一单元电力线和第二单元电力线的存储器阵列。 当控制信号处于第一状态时，电源控制电路分别向第一单元电力线和第二电力线输出第一电源电压和第二电源电压，并将中间电压输出到第一单元电力线 以及当控制信号处于第二状态时的第二单元电力线。

公开(公告)号：US20130272058A1

公开(公告)日：2013-10-17

申请号：US13874834

申请日：2013-05-01

Applicant: Renesas Electronics Corporation

Inventor： Noriaki MAEDA ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC: G11C11/412 ,  G11C11/419

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

公开(公告)号：US09123435B2

公开(公告)日：2015-09-01

申请号：US13874834

申请日：2013-05-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Noriaki Maeda ,  Yoshihiro Shinozaki ,  Masanao Yamaoka ,  Yasuhisa Shimazaki ,  Masanori Isoda ,  Koji Nii

IPC: G11C11/00 ,  G11C11/412 ,  G11C5/06 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.