公开(公告)号：US20160211246A1

公开(公告)日：2016-07-21

申请号：US14733776

申请日：2015-06-08

Applicant: Renesas Electronics Corporation

Inventor： Satoru AKIYAMA ,  Hiroyoshi KOBAYASHI ,  Hisao INOMATA ,  Sei SAITOU

IPC: H01L25/18 ,  H01L29/808 ,  H01L23/498 ,  H01L29/16 ,  H01L29/20 ,  H01L23/495 ,  H01L29/78 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/78 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2924/181 ,  H03F1/223 ,  H03F1/226 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

Abstract translation: 提高了半导体器件的制造成品率。 提供了一种共源共栅耦合系统的半导体器件，该半导体器件配备有多个使用材料的常闭结FET，比硅更大的带隙物质，以及使用硅作为材料的常关MOSFET。 此时，半导体芯片具有以分割方式形成有结结FET的多个结型FET半导体芯片（半导体芯片CHP0和半导体芯片CHP1）以及与MOSFET形成的MOSFET半导体芯片（半导体芯片CHP2）。

公开(公告)号：US20130335134A1

公开(公告)日：2013-12-19

申请号：US13909293

申请日：2013-06-04

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamitsu KANAZAWA ,  Satoru AKIYAMA

IPC: H01L27/088 ,  H03K3/012 ,  H01L29/16

CPC classification number: H01L27/0883 ,  H01L23/49562 ,  H01L23/49575 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/7827 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02P27/06 ,  H03K3/012 ,  H03K17/102 ,  H03K17/107 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set in an OFF state.

Abstract translation: 存在配置有级联耦合的通常的JFET和常关MOSFET的半导体器件可能由于错误导通等而断裂的可能性。半导体器件配置有常导SiCJFET和常关 Si型MOSFET。 常闭SiCJFET和常关Si型MOSFET级联耦合并配置开关电路。 根据一个输入信号，常控SiCJFET和常关Si型MOSFET被控制成具有将两个晶体管设置在OFF状态的周期。

公开(公告)号：US20180166430A1

公开(公告)日：2018-06-14

申请号：US15894564

申请日：2018-02-12

Applicant: Renesas Electronics Corporation

Inventor： Satoru AKIYAMA ,  Hiroyoshi KOBAYASHI ,  Hisao INOMATA ,  Sei SAITOU

IPC: H01L25/18 ,  H01L21/82 ,  H03F1/22 ,  H01L23/498 ,  H01L23/495 ,  H01L29/808 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L25/18 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/78 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2924/13091 ,  H01L2924/181 ,  H03F1/223 ,  H03F1/226 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.

公开(公告)号：US20150255455A1

公开(公告)日：2015-09-10

申请号：US14720121

申请日：2015-05-22

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takamitsu KANAZAWA ,  Satoru AKIYAMA

IPC: H01L27/088 ,  H02P27/06 ,  H03K17/567 ,  H01L27/098 ,  H03K3/012

CPC classification number: H01L27/0883 ,  H01L23/49562 ,  H01L23/49575 ,  H01L27/098 ,  H01L29/1608 ,  H01L29/7827 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49111 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/30107 ,  H01L2924/3011 ,  H02P27/06 ,  H03K3/012 ,  H03K17/102 ,  H03K17/107 ,  H03K17/567 ,  H03K2017/6875 ,  H01L2924/00014 ,  H01L2924/00

Abstract: There exists a possibility that a semiconductor device configured with a normally-on JFET and a normally-off MOSFET which are coupled in cascade may break by erroneous conduction, etc. A semiconductor device is configured with a normally-on SiCJFET and a normally-off Si-type MOSFET. The normally-on SiCJFET and the normally-off Si-type MOSFET are coupled in cascade and configure a switching circuit. According to one input signal, the normally-on SiCJFET and the normally-off Si-type MOSFET are controlled so as to have a period in which both transistors are set to an OFF state.

Abstract translation: 存在配置有级联耦合的通常的JFET和常关MOSFET的半导体器件可能由于错误导通等而断裂的可能性。半导体器件配置有常导SiCJFET和常关 Si型MOSFET。 常闭SiCJFET和常关Si型MOSFET级联耦合并配置开关电路。 根据一个输入信号，常控SiCJFET和常关Si型MOSFET被控制为具有两个晶体管被设置为截止状态的周期。