公开(公告)号：US20160211246A1

公开(公告)日：2016-07-21

申请号：US14733776

申请日：2015-06-08

Applicant: Renesas Electronics Corporation

Inventor： Satoru AKIYAMA ,  Hiroyoshi KOBAYASHI ,  Hisao INOMATA ,  Sei SAITOU

IPC: H01L25/18 ,  H01L29/808 ,  H01L23/498 ,  H01L29/16 ,  H01L29/20 ,  H01L23/495 ,  H01L29/78 ,  H01L23/31

CPC classification number: H01L25/18 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/78 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2924/181 ,  H03F1/223 ,  H03F1/226 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The manufacturing yield of a semiconductor device is improved. There is provided a semiconductor device of a cascode coupling system, which is equipped with a plurality of normally-on junction FETs using as a material, a substance larger in bandgap than silicon, and a normally-off MOSFET using silicon as a material. At this time, the semiconductor chip has a plurality of junction FET semiconductor chips (semiconductor chip CHP0 and semiconductor chip CHP1) formed with the junction FETs in a divided fashion, and a MOSFET semiconductor chip (semiconductor chip CHP2) formed with the MOSFET.

Abstract translation: 提高了半导体器件的制造成品率。 提供了一种共源共栅耦合系统的半导体器件，该半导体器件配备有多个使用材料的常闭结FET，比硅更大的带隙物质，以及使用硅作为材料的常关MOSFET。 此时，半导体芯片具有以分割方式形成有结结FET的多个结型FET半导体芯片（半导体芯片CHP0和半导体芯片CHP1）以及与MOSFET形成的MOSFET半导体芯片（半导体芯片CHP2）。

公开(公告)号：US20180076286A1

公开(公告)日：2018-03-15

申请号：US15652389

申请日：2017-07-18

Applicant: Renesas Electronics Corporation

Inventor： Hisao INOMATA

IPC: H01L29/10 ,  H01L21/04 ,  H01L21/265 ,  H01L21/28 ,  H01L21/3215 ,  H01L21/3205 ,  H01L29/16 ,  H01L29/20 ,  H01L21/266 ,  H01L29/808 ,  H01L29/66

CPC classification number: H01L29/1058 ,  H01L21/046 ,  H01L21/047 ,  H01L21/049 ,  H01L21/26546 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28264 ,  H01L21/32055 ,  H01L21/3215 ,  H01L29/1066 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/36 ,  H01L29/66068 ,  H01L29/66909 ,  H01L29/66924 ,  H01L29/8083

Abstract: A semiconductor device includes: a first-conductivity-type semiconductor substrate serving as a drain layer; a first-conductivity-type epitaxial layer formed on the semiconductor substrate; a first-conductivity-type source layer formed in a surface part of the epitaxial layer; two second-conductivity-type gate layers formed in the surface part of the epitaxial layer so as to sandwich the source layer; a first-conductivity-type channel forming layer formed so as to be sandwiched between the two gate layers, the first-conductivity-type channel forming layer being formed on an inner side of the source layer in the epitaxial layer; and an electrode connected to one of the drain layer, the source layer, and the gate layer. In the channel forming layer, two first-conductivity-type impurity layers each having a substantially predetermined width are formed adjacent to each other in a direction crossing a channel.

公开(公告)号：US20180166430A1

公开(公告)日：2018-06-14

申请号：US15894564

申请日：2018-02-12

Applicant: Renesas Electronics Corporation

Inventor： Satoru AKIYAMA ,  Hiroyoshi KOBAYASHI ,  Hisao INOMATA ,  Sei SAITOU

IPC: H01L25/18 ,  H01L21/82 ,  H03F1/22 ,  H01L23/498 ,  H01L23/495 ,  H01L29/808 ,  H01L29/16 ,  H01L29/20 ,  H01L29/78

CPC classification number: H01L25/18 ,  H01L21/8213 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49562 ,  H01L23/49575 ,  H01L23/49844 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/78 ,  H01L29/808 ,  H01L2224/0603 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2924/13091 ,  H01L2924/181 ,  H03F1/223 ,  H03F1/226 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A semiconductor device, including a first semiconductor chip including a first substrate having a semiconductor larger in bandgap than silicon, the first semiconductor chip being formed with a first FET including a first gate electrode, a first source, and a first drain, a second semiconductor chip including a second substrate having a semiconductor larger in bandgap than silicon, the second semiconductor chip being formed with a second FET having a second gate electrode, a second source, and a second drain, and a third semiconductor chip including a third substrate having silicon, the third semiconductor chip being formed with a MOSFET including a third gate electrode, a third source, and a third drain. The first semiconductor chip and the second semiconductor chip are mounted over a first chip mounting section, and the third semiconductor chip is mounted over a second chip mounting section.